Pr3Si6N11/Si3N4 stacked high-k gate dielectrics with high quality ultrathin Si3N 4 interfacial layers

Tadahiro Ohmi, Hidetoshi Wakamatsu, Akinobu Teramoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

In Order to utilize the entire capability of the silicon crystal, we must fabricate LSI on any crystal orientation silicon surface using three dimensional structure MOS transistors, i.e., very high integrity gate insulator films must be formed on any crystal orientation silicon surface with the same formation speed, i.e., the radical oxidation (SiO2) and the radical nitridation (Si3N4) at low temperatures. Accumulation mode balanced CMOS fabricated on (551) surface silicon SOI substrate has been theoretically confirmed to exhibit super high speed performance over 100 GHz clock rate at 45 nm technology node where the gate insulator film to silicon interface is atomically flat and the series resistance of the source and the drain electrode is decreased by a factor of two orders of magnitude by introducing very low contact resistance new suicide materials to n+ region (ErSi 2) and p+ region (Pr2Si), respectively.

Original languageEnglish
Title of host publicationSilicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications
Pages275-284
Number of pages10
Edition2
DOIs
Publication statusPublished - 2011 Aug 1
EventSilicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications - 219th ECS Meeting - Montreal, QC, Canada
Duration: 2011 May 22011 May 4

Publication series

NameECS Transactions
Number2
Volume35
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

OtherSilicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications - 219th ECS Meeting
CountryCanada
CityMontreal, QC
Period11/5/211/5/4

ASJC Scopus subject areas

  • Engineering(all)

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