Prototype fabrication of field-programmable digital filter LSIs using multiple-valued current-mode logic - Device scaling and future prospects

Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journalArticlepeer-review

Abstract

This paper presents prototype design and fabrication of Field-Programmable Digital Filter (FPDF) LSIs, which employ carry-propagation-free redundant arithmetic algorithms for faster operation and Multiple-Valued Current-Mode Logic (MV-CML) for high-density low-power implementation. The original contribution of this paper is to evaluate, through actual chip fabrication, the potential impacts of MV-CML circuit technology on hardware reduction in programmable LSIs. The prototype FPDF fabrication with 0.6μm and 0.35μm CMOS technology demonstrates that the chip area and power consumption can be significantly reduced, compared with the standard binary logic implementation. Major problems associated with device scaling are also analyzed to discuss future prospects of MV-CML technology.

Original languageEnglish
Pages (from-to)545-565
Number of pages21
JournalJournal of Multiple-Valued Logic and Soft Computing
Volume11
Issue number5-6
Publication statusPublished - 2005 Aug 15

Keywords

  • FIR filters
  • FPGAs
  • Multiple-valued logic
  • Signal processor

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Logic

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