Prospects of multiple-valued associative VLSI processors

Takahiro Hanyu, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution


This paper presents a design of a high-density multiple-valued content-addressable memory (CAM) and its application to VLSI processors. The basic search operations executed in the multiple-valued CAM are both the threshold operations in each cell and logic-value conversion against a multiple-valued input data. Various multiple-valued operations for data retrieval can be easily performed by programming logic-value conversion. Moreover, the cell circuit consists of two transistors and one capacitance, which are used for not only the storage of multilevel charge, but also for linear sum operation by the capacitive coupling technique. Finally, several approaches for developing application-specific CAM architectures to support real-time artificial inference features in intelligent robot systems are demonstrated.

Original languageEnglish
Title of host publicationMidwest Symposium on Circuits and Systems
PublisherPubl by IEEE
Number of pages5
ISBN (Print)0780317610
Publication statusPublished - 1993 Dec 1
EventProceedings of the 36th Midwest Symposium on Circuits and Systems - Detroit, MI, USA
Duration: 1993 Aug 161993 Aug 18

Publication series

NameMidwest Symposium on Circuits and Systems


OtherProceedings of the 36th Midwest Symposium on Circuits and Systems
CityDetroit, MI, USA

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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