Proposal of area-arrayed bump joint structures for minimizing residual stress in stacked silicon chips mounted by flip chip technology

Nobuki Ueta, Takuya Sasaki, Hideo Miura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Since mechanical stress sometimes degrades both electronic functions and reliability of LSI chips, it is very important to control the residual stress in them to assure their highly reliable performance. The authors have already found that the distribution of the residual stress on a transistor formation surface of a chip changes significantly by changing the bump joint structure of packages or modules from a wire-bonding structure to an area-arrayed flip-chip structure. In addition, a periodic stress distribution appears due to the periodic alignment of metallic bumps. We have found that the dominant structural factors that determine the residual stress are the thickness of a chip, thermal expansion coefficient of underfill material and the diameter, pitch and the relative position of bumps in each joint layer. In addition, we have proposed the optimum stacke structure for the synchronous bump alignment structure such as memory-stacked structures to minimize the local residual stress in each stacked chip. In this study, the changes of the electronic performance of NMOS transistors and capacitors caused by mechanical stress were measured by applying a four-point bending method. The change rate of the transconductance of NMOS transistors increased to about 15%/100-MPa by decreasing the gate length from 400 nm to 150 nm. The relative permittivity of HfD2 also changed by about 4%/1 %-strain. In addition, we propose a new bump joint structure for minimizing the residual stress considering the local structure near TSV (Through Silicon Via) using a finite element analysis. When all the bumps are jointed to TSV directly, the amplitude of the local residual stress of a chip is about 200 MPa. On the other hand, when the bumps are connected to the TSV through interconnection thin films, the amplitude of the local residual stress of a chip decreases to about 0 MPa. Therefore, it is very important to optimize the relative position between bumps and vias. Also, it is possible to minimize the local residual stress of the chips in three-dimensionally stacked structures to make a stressrelaxation layer using the material with low elastic modulus. Therefore, it is important to optimize the assembly structure of the three-dimensionally stacked LSI chips for minimizing the change of electronic performance ofdevices.

Original languageEnglish
Title of host publication2008 10th International Conference on Electronic Materials and Packaging, EMAP 2008
Pages228-231
Number of pages4
DOIs
Publication statusPublished - 2008 Dec 1
Event2008 10th International Conference on Electronic Materials and Packaging, EMAP 2008 - Taipei, Taiwan, Province of China
Duration: 2008 Oct 222008 Oct 24

Publication series

Name2008 10th International Conference on Electronic Materials and Packaging, EMAP 2008

Other

Other2008 10th International Conference on Electronic Materials and Packaging, EMAP 2008
Country/TerritoryTaiwan, Province of China
CityTaipei
Period08/10/2208/10/24

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Mechanical Engineering

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