Proposal of a multi-layer channel MOSFET: The application of selective etching for Si/SiGe stacked layers

D. Sasaki, S. Ohmi, M. Sakuraba, J. Murota, T. Sakai

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)

Abstract

A multi-layer channel MOSFET (ML-MOSFET) and its fabrication process were proposed for future CMOS application. ML-MOSFET has multi-Si channel layers stacked vertically, so that the drain current per 1 μm gate width on wafer is expected to increase with the number of channel layers compared to conventional double-gate MOSFET. I on = 3.9 mA/μm was obtained for ML-MOSFET with three Si channel layers (L g : 10 nm, T Si : 2.5 nm) by the device simulation. Fabrication process of multi-layer channel using selective etching for SiGe/Si stacked layers was also investigated.

Original languageEnglish
Pages (from-to)270-273
Number of pages4
JournalApplied Surface Science
Volume224
Issue number1-4
DOIs
Publication statusPublished - 2004 Mar 15

Keywords

  • Current drivability
  • Double gate
  • MOSFET
  • Multi-layer channel
  • SiGe selective etching
  • Three-dimensional structure

ASJC Scopus subject areas

  • Chemistry(all)
  • Condensed Matter Physics
  • Physics and Astronomy(all)
  • Surfaces and Interfaces
  • Surfaces, Coatings and Films

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