Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure

Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Citations (Scopus)

Abstract

A field programmable Very large scale integrators (VLSI) processor (FPVLSI) based on a bit-serial mesh-connected cellular array that reduces complexity of a programmable interconnection network was discussed. It was observed that The BPE processing time in the FPVLSI was only 1.4 times longer than that of the Field-programmable gate arrays (FPGA). The number of FPVLSI BPEs available in the chip was found to be 13 times larger than that of FPGA BPEs. It was found that the total throughput of the FPVLSI-based FFT was 9 times higher than that of the FPGA-based FFT.

Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publicationEmerging Trends in VLSI Systems Design
EditorsA. Smailagic, M. Bayoumi
Pages258-259
Number of pages2
DOIs
Publication statusPublished - 2004 Sep 24
EventProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design - Lafayette, LA, United States
Duration: 2004 Feb 192004 Feb 20

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Other

OtherProceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
CountryUnited States
CityLafayette, LA
Period04/2/1904/2/20

ASJC Scopus subject areas

  • Engineering(all)

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