TY - GEN
T1 - Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure
AU - Ohsawa, Naotaka
AU - Sakamoto, Osamu
AU - Hariyama, Masanori
AU - Kameyama, Michitaka
PY - 2004/9/24
Y1 - 2004/9/24
N2 - A field programmable Very large scale integrators (VLSI) processor (FPVLSI) based on a bit-serial mesh-connected cellular array that reduces complexity of a programmable interconnection network was discussed. It was observed that The BPE processing time in the FPVLSI was only 1.4 times longer than that of the Field-programmable gate arrays (FPGA). The number of FPVLSI BPEs available in the chip was found to be 13 times larger than that of FPGA BPEs. It was found that the total throughput of the FPVLSI-based FFT was 9 times higher than that of the FPGA-based FFT.
AB - A field programmable Very large scale integrators (VLSI) processor (FPVLSI) based on a bit-serial mesh-connected cellular array that reduces complexity of a programmable interconnection network was discussed. It was observed that The BPE processing time in the FPVLSI was only 1.4 times longer than that of the Field-programmable gate arrays (FPGA). The number of FPVLSI BPEs available in the chip was found to be 13 times larger than that of FPGA BPEs. It was found that the total throughput of the FPVLSI-based FFT was 9 times higher than that of the FPGA-based FFT.
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U2 - 10.1109/ISVLSI.2004.1339547
DO - 10.1109/ISVLSI.2004.1339547
M3 - Conference contribution
AN - SCOPUS:4544292826
SN - 0769520979
SN - 9780769520971
T3 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
SP - 258
EP - 259
BT - Proceedings - IEEE Computer Society Annual Symposium on VLSI
A2 - Smailagic, A.
A2 - Bayoumi, M.
T2 - Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
Y2 - 19 February 2004 through 20 February 2004
ER -