Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure

Naotaka Ohsawa; Osamu Sakamoto; Masanori Hariyama; Michitaka Kameyama

doi:10.1109/ISVLSI.2004.1339547

Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure

Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

21 Citations (Scopus)

Abstract

A field programmable Very large scale integrators (VLSI) processor (FPVLSI) based on a bit-serial mesh-connected cellular array that reduces complexity of a programmable interconnection network was discussed. It was observed that The BPE processing time in the FPVLSI was only 1.4 times longer than that of the Field-programmable gate arrays (FPGA). The number of FPVLSI BPEs available in the chip was found to be 13 times larger than that of FPGA BPEs. It was found that the total throughput of the FPVLSI-based FFT was 9 times higher than that of the FPGA-based FFT.

Original language	English
Title of host publication	Proceedings - IEEE Computer Society Annual Symposium on VLSI
Subtitle of host publication	Emerging Trends in VLSI Systems Design
Editors	A. Smailagic, M. Bayoumi
Pages	258-259
Number of pages	2
DOIs	https://doi.org/10.1109/ISVLSI.2004.1339547
Publication status	Published - 2004 Sep 24
Event	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design - Lafayette, LA, United States Duration: 2004 Feb 19 → 2004 Feb 20

Publication series

Name	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design

Other

Other	Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design
Country/Territory	United States
City	Lafayette, LA
Period	04/2/19 → 04/2/20

ASJC Scopus subject areas

Engineering(all)

Access to Document

10.1109/ISVLSI.2004.1339547

Cite this

Ohsawa, N., Sakamoto, O., Hariyama, M., & Kameyama, M. (2004). Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure. In A. Smailagic, & M. Bayoumi (Eds.), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design (pp. 258-259). (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design). https://doi.org/10.1109/ISVLSI.2004.1339547

Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure. / Ohsawa, Naotaka; Sakamoto, Osamu; Hariyama, Masanori; Kameyama, Michitaka.

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. ed. / A. Smailagic; M. Bayoumi. 2004. p. 258-259 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ohsawa, N, Sakamoto, O, Hariyama, M & Kameyama, M 2004, Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure. in A Smailagic & M Bayoumi (eds), Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, pp. 258-259, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design, Lafayette, LA, United States, 04/2/19. https://doi.org/10.1109/ISVLSI.2004.1339547

Ohsawa N, Sakamoto O, Hariyama M, Kameyama M. Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure. In Smailagic A, Bayoumi M, editors, Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. 2004. p. 258-259. (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design). https://doi.org/10.1109/ISVLSI.2004.1339547

Ohsawa, Naotaka ; Sakamoto, Osamu ; Hariyama, Masanori ; Kameyama, Michitaka. / Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure. Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design. editor / A. Smailagic ; M. Bayoumi. 2004. pp. 258-259 (Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging Trends in VLSI Systems Design).

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Program-counter-less bit-serial field-programmable VLSI processor with mesh-connected cellular array structure

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