Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure

Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda, Atsushi Shimizu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This article consists of a collection of slides from the authors' conference presentation. Some of the topics discussed include: Introduction and Background; NARA Architecture; NARA Key Features and Functions; NARA Chip Implementation; Target Applications; Conclusion.

Original languageEnglish
Title of host publication2015 IEEE Hot Chips 27 Symposium, HCS 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467388856
DOIs
Publication statusPublished - 2015 May 23
Externally publishedYes
Event27th IEEE Hot Chips Symposium, HCS 2015 - Cupertino, United States
Duration: 2015 Aug 222015 Aug 25

Publication series

Name2015 IEEE Hot Chips 27 Symposium, HCS 2015

Conference

Conference27th IEEE Hot Chips Symposium, HCS 2015
Country/TerritoryUnited States
CityCupertino
Period15/8/2215/8/25

ASJC Scopus subject areas

  • Hardware and Architecture

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