TY - GEN
T1 - Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure
AU - Iwasaki, Hiroe
AU - Onishi, Takayuki
AU - Nakamura, Ken
AU - Nitta, Koyo
AU - Sano, Takashi
AU - Nishida, Yukikuni
AU - Yokohari, Kazuya
AU - Su, Jia
AU - Ono, Naoki
AU - Kusaba, Ritsu
AU - Sagata, Atsushi
AU - Ikeda, Mitsuo
AU - Shimizu, Atsushi
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/5/23
Y1 - 2015/5/23
N2 - This article consists of a collection of slides from the authors' conference presentation. Some of the topics discussed include: Introduction and Background; NARA Architecture; NARA Key Features and Functions; NARA Chip Implementation; Target Applications; Conclusion.
AB - This article consists of a collection of slides from the authors' conference presentation. Some of the topics discussed include: Introduction and Background; NARA Architecture; NARA Key Features and Functions; NARA Chip Implementation; Target Applications; Conclusion.
UR - http://www.scopus.com/inward/record.url?scp=84980315818&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84980315818&partnerID=8YFLogxK
U2 - 10.1109/HOTCHIPS.2015.7477464
DO - 10.1109/HOTCHIPS.2015.7477464
M3 - Conference contribution
AN - SCOPUS:84980315818
T3 - 2015 IEEE Hot Chips 27 Symposium, HCS 2015
BT - 2015 IEEE Hot Chips 27 Symposium, HCS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 27th IEEE Hot Chips Symposium, HCS 2015
Y2 - 22 August 2015 through 25 August 2015
ER -