PROCESS TECHNOLOGIES FOR HIGH DENSITY, HIGH SPEED 16 MEGABIT DYNAMIC RAM.

F. Horiguchi, A. Nitayama, K. Hieda, T. Hamamoto, K. Tsuda, K. Sunouchi, N. Takenouchi, S. Aritome, H. Takato, M. Kimura, K. Yamabe, M. Nakase, Y. Kamata, F. Masuoka

Research output: Contribution to journalConference articlepeer-review

9 Citations (Scopus)

Abstract

Key points of submicrometer CMOS technologies for fabrication of an experimental 16-Mb DRAM (dynamic random-access memory) are discussed. The memory cell and the transistor designs are most important to realize high-density, high-speed DRAMs. The main features of the technology are a buried stacked capacitor cell and a high speed CMOS structure. The lithographic levels used for critical layers were 0. 7 mu m. The technologies have been verified using test vehicles and an experimental 16-Mb DRAM.

Original languageEnglish
Pages (from-to)324-327
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
DOIs
Publication statusPublished - 1987

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

Fingerprint Dive into the research topics of 'PROCESS TECHNOLOGIES FOR HIGH DENSITY, HIGH SPEED 16 MEGABIT DYNAMIC RAM.'. Together they form a unique fingerprint.

Cite this