TY - JOUR
T1 - PROCESS TECHNOLOGIES FOR HIGH DENSITY, HIGH SPEED 16 MEGABIT DYNAMIC RAM.
AU - Horiguchi, F.
AU - Nitayama, A.
AU - Hieda, K.
AU - Hamamoto, T.
AU - Tsuda, K.
AU - Sunouchi, K.
AU - Takenouchi, N.
AU - Aritome, S.
AU - Takato, H.
AU - Kimura, M.
AU - Yamabe, K.
AU - Nakase, M.
AU - Kamata, Y.
AU - Masuoka, F.
PY - 1987
Y1 - 1987
N2 - Key points of submicrometer CMOS technologies for fabrication of an experimental 16-Mb DRAM (dynamic random-access memory) are discussed. The memory cell and the transistor designs are most important to realize high-density, high-speed DRAMs. The main features of the technology are a buried stacked capacitor cell and a high speed CMOS structure. The lithographic levels used for critical layers were 0. 7 mu m. The technologies have been verified using test vehicles and an experimental 16-Mb DRAM.
AB - Key points of submicrometer CMOS technologies for fabrication of an experimental 16-Mb DRAM (dynamic random-access memory) are discussed. The memory cell and the transistor designs are most important to realize high-density, high-speed DRAMs. The main features of the technology are a buried stacked capacitor cell and a high speed CMOS structure. The lithographic levels used for critical layers were 0. 7 mu m. The technologies have been verified using test vehicles and an experimental 16-Mb DRAM.
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U2 - 10.1109/iedm.1987.191422
DO - 10.1109/iedm.1987.191422
M3 - Conference article
AN - SCOPUS:0023544148
SP - 324
EP - 327
JO - Technical Digest - International Electron Devices Meeting
JF - Technical Digest - International Electron Devices Meeting
SN - 0163-1918
ER -