Process integration for 64 M DRAM using an asymmetrical stacked trench capacitor (AST) cell

K. Sunouchi, F. Horiguchi, A. Nitayama, K. Hieda, H. Takato, N. Okabe, T. Yamada, T. Ozaki, K. Hashimoto, S. Takedai, A. Yagishita, A. Kumagae, Y. Takahashi, F. Masuoka

Research output: Contribution to journalConference articlepeer-review

10 Citations (Scopus)


The key points of sub-half-micron CMOS technologies for 64-Mb DRAM fabrication are described. The main features of the technologies are (1) an asymmetrical stacked trench capacitor (AST) cell, (2) localized channel implantation through the field oxide (LIF), and (3) a 0.4-μm transistor with LDD (lightly doped drain) n- impurity of arsenic. The lithographic levels are 0.4 μm for critical layers, achieved using a KrF excimer laser stepper. The AST cell has a stacked capacitor in a trench; the trenches are located asymmetrically with respect to each other. A small cell area of 1.53 μm2 has been achieved by adopting the LIF isolation and the As LDD transistor for the AST cell. An experimental 64-Mb DRAM chip has been successfully fabricated using these technologies.

Original languageEnglish
Pages (from-to)647-650
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting
Publication statusPublished - 1990 Dec 1
Event1990 International Electron Devices Meeting - San Francisco, CA, USA
Duration: 1990 Dec 91990 Dec 12

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry


Dive into the research topics of 'Process integration for 64 M DRAM using an asymmetrical stacked trench capacitor (AST) cell'. Together they form a unique fingerprint.

Cite this