We have developed a novel integration scheme for FCRAM cores using a high-dielectric capacitor technology and low-temperature process technology so we can scale the design rule towards 0.13 μm and improve device performance. Ru/Ta2O5/Ru capacitor technology, which can provide a dielectric constant as high as 70 and an SiO2-equivalent thickness of 0.7 nm, has been established combined with a robust cylinder electrode fabrication process using a TiN liner. A self-aligned storage-node contact fabrication process with low-temperature (600°C) Si3N4 deposition improves the transistor performance by more than 10%. These technologies have been applied to a 0.13 μm-generation device, and the functionality of this device has been confirmed. Also, this paper demonstrates the scalability of these technologies to the 0.1 μm generation.
|Number of pages||10|
|Journal||Fujitsu Scientific and Technical Journal|
|Publication status||Published - 2003 Aug 14|
ASJC Scopus subject areas
- Human-Computer Interaction
- Hardware and Architecture
- Electrical and Electronic Engineering