Pre-distortion linearizer using self base bias control circuit

Shintaro Shinjo, Kazuyuki Totano, Hiroyuki Tokunaga, Kazutomi Mori, Noriharu Suematsu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The pre-distortion linearizer, which is composed of a RF transistor with a self base bias control circuit, is described. By applying the p-MOSFET current mirror circuit to the self base bias control circuit, the linearizer responds the envelope of the modulated signal. The linearizer realizes both positive and negative gain deviations, and compensates the distortion of any PA's. The GaAs FET power amplifier (PA), which has negative gain deviation, achieves the adjacent channel power leakage ratio (ACLR) improvement of 8.1dB by using the proposed linearizer for QPSK modulated signal with the chip rate of 3.84Mc/s. Also, the LDMOS PA, which has positive gain deviation, achieves the ACLR improvement of 8.3dB.

Original languageEnglish
Title of host publication2006 Asia-Pacific Microwave Conference Proceedings, APMC
Pages879-882
Number of pages4
DOIs
Publication statusPublished - 2006 Dec 1
Externally publishedYes
Event2006 Asia-Pacific Microwave Conference, APMC - Yokohama, Japan
Duration: 2006 Dec 122006 Dec 15

Publication series

NameAsia-Pacific Microwave Conference Proceedings, APMC
Volume2

Other

Other2006 Asia-Pacific Microwave Conference, APMC
CountryJapan
CityYokohama
Period06/12/1206/12/15

Keywords

  • Distortion
  • Linearizer
  • Power amplifiers
  • Silicon germanium

ASJC Scopus subject areas

  • Engineering(all)

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  • Cite this

    Shinjo, S., Totano, K., Tokunaga, H., Mori, K., & Suematsu, N. (2006). Pre-distortion linearizer using self base bias control circuit. In 2006 Asia-Pacific Microwave Conference Proceedings, APMC (pp. 879-882). [4429553] (Asia-Pacific Microwave Conference Proceedings, APMC; Vol. 2). https://doi.org/10.1109/APMC.2006.4429553