@inbook{46d1bee49db54f688ab854322d00805b,
title = "Power-aware dynamic cache partitioning for CMPs",
abstract = "Cache partitioning and power-gating schemes are major research topics to achieve a high-performance and low-power shared cache for next generation chip multiprocessors(CMPs). We propose a poweraware cache partitioning mechanism, which is a scheme to realize both low power and high performance using power-gating and cache partitioning at the same time. The proposed cache mechanism is composed of a way-allocation function and power control function; each function works based on the cache locality assessment. The performance evaluation results show that the proposed cache mechanism with a performanceoriented parameter setting can reduce energy consumption by 20% while keeping the performance, and the mechanism with an energy-oriented parameter setting can reduce 54% energy consumption with a performance degradation of 13%. The hardware implementation results indicate that the delay and area overheads to control the proposed mechanism are negligible, and therefore hardly affect both the entire chip design and performance.",
author = "Isao Kotera and Kenta Abe and Ryusuke Egawa and Hiroyuki Takizawa and Hiroaki Kobayashi",
year = "2011",
month = apr,
day = "28",
doi = "10.1007/978-3-642-19448-1_8",
language = "English",
isbn = "9783642194474",
series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",
pages = "135--153",
editor = "Per Stenstrom",
booktitle = "Transactions on High-Performance Embedded Architectures and Compilers III",
}