Power analysis on unrolled architecture with points-of-interest search and its application to prince block cipher

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

This paper explores the feasibility of power analysis attacks against low-latency block ciphers implemented with unrolled architectures capable of encryption/decryption in a single clock cycle. Unrolled archi- tectures have been expected to be somewhat resistant against side-channel attacks compared to typical loop architectures because of no memory (i.e. register) element storing intermediate results in a synchronous manner. In this paper, we present a systematic method for selecting Points-of-Interest for power analysis on unrolled architectures as well as calculating dynamic power consumption at a target function. Then, we apply the proposed method to PRINCE, which is known as one of the most efficient low-latency ciphers, and evaluate its validity with an experiment using a set of unrolled PRINCE processors implemented on an FPGA. Finally, a countermeasure against such analysis is discussed.

Original languageEnglish
Pages (from-to)149-157
Number of pages9
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE100A
Issue number1
DOIs
Publication statusPublished - 2017 Jan

Keywords

  • Cryptographic hardware
  • Low latency ciphers
  • Power analysis
  • Side-channel attacks
  • Unrolled architectures

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Fingerprint Dive into the research topics of 'Power analysis on unrolled architecture with points-of-interest search and its application to prince block cipher'. Together they form a unique fingerprint.

  • Cite this