Pixel scaling in complementary metal oxide silicon image sensor with lateral overflow integration capacitor

Two wide dynamic range (DR) complementary metal oxide silicon (CMOS) image sensors (CIS) with lateral overflow integration capacitor (LOFIC) have been developed in order to scale down the pixel size. A checker-pattern CIS has achieved high area-efficiency for the full well capacity (FWC) by introducing the rectangle structure and placing the color-filters and on-chip microlens along the direction at an angle of 45°. A shared two pixels CIS has achieved small pixel pitch by introducing a lateral overflow gate that overflows over-saturated photoelectrons from the photodiode to the LOFIC directly. These CISs were fabricated using the 0.18-mm 2-polycrystalline 3-metal CMOS technology with buried-pinnedphotodiode process and achieved the high FWC, low noise, wide DR and high resolution performances. These structures are effective for obtaining the small pixel size with the advantageous characteristics of LOFIC CIS. In this paper, these structures, operation methods and measurement results of these CISs have been discussed.