Pipe-shaped BiCS flash memory with 16 stacked layers and multi-level-cell operation for ultra high density storage devices

Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kido, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Yuzo Nagata, Li Zhang, Yoshihisa Iwata, Ryouhei Kirisawa, Hideaki Aochi, Akihiro Nitayama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

256 Citations (Scopus)

Abstract

We propose Pipe-shaped Bit Cost Scalable (P-BiCS) flash memory which consists of pipe-shaped NAND strings folded like a U-shape instead of the straight-shape. P-BiCS flash technology achieves a highly reliable memory film of which the program and erase (P/E) operation is managed by Fowler-Nordheim (FN) tunneling, that is originated by the strong curvature effect of its small pipe radius, a low resistance source line by the layered metal wirings and a tightly controlled diffusion profile for the select-gate (SG) transistor due to low thermal budget. The effective 1-bit cell area of 0.00082 um2 and its functionality are successfully demonstrated using the 32 Gbit test chip with the 3-dimensionally 16 stacked layers and the Multi-Level-Cell (MLC) operation by 60nm P-BiCS flash technology.

Original languageEnglish
Title of host publication2009 Symposium on VLSI Technology, VLSIT 2009
Pages136-137
Number of pages2
Publication statusPublished - 2009 Nov 16
Event2009 Symposium on VLSI Technology, VLSIT 2009 - Kyoto, Japan
Duration: 2009 Jun 162009 Jun 18

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2009 Symposium on VLSI Technology, VLSIT 2009
CountryJapan
CityKyoto
Period09/6/1609/6/18

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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