Physics of interfaces between gate electrodes and high-k dielectrics

K. Shiraishi, H. Takeuchi, Y. Akasaka, T. Nakayama, S. Miyazaki, T. Nakaoka, A. Ohta, H. Watanabe, N. Umezawa, K. Ohmori, P. Ahmet, K. Toii, T. Chikyow, Y. Nara, T. J.King Liu, H. Iwai, K. Yamada

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high- and low-work-function materials is governed by the O vacancy and O interstitial generation, respectively. From our theoretical considerations, we have found that the work-function pinning-free-region generally appears due to me difference in the mechanism of Fermi-level pinning of high- and low-work-function materials. Further, we also discuss the interface physics between pure metal gates and high-k dielectrics.

Original languageEnglish
Title of host publicationICSICT-2006
Subtitle of host publication2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
PublisherIEEE Computer Society
Pages384-387
Number of pages4
ISBN (Print)1424401615, 9781424401611
DOIs
Publication statusPublished - 2006
EventICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
Duration: 2006 Oct 232006 Oct 26

Publication series

NameICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

OtherICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
CountryChina
CityShanghai
Period06/10/2306/10/26

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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