TY - GEN
T1 - Physics of interfaces between gate electrodes and high-k dielectrics
AU - Shiraishi, K.
AU - Takeuchi, H.
AU - Akasaka, Y.
AU - Nakayama, T.
AU - Miyazaki, S.
AU - Nakaoka, T.
AU - Ohta, A.
AU - Watanabe, H.
AU - Umezawa, N.
AU - Ohmori, K.
AU - Ahmet, P.
AU - Toii, K.
AU - Chikyow, T.
AU - Nara, Y.
AU - Liu, T. J.King
AU - Iwai, H.
AU - Yamada, K.
PY - 2006
Y1 - 2006
N2 - Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high- and low-work-function materials is governed by the O vacancy and O interstitial generation, respectively. From our theoretical considerations, we have found that the work-function pinning-free-region generally appears due to me difference in the mechanism of Fermi-level pinning of high- and low-work-function materials. Further, we also discuss the interface physics between pure metal gates and high-k dielectrics.
AB - Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high- and low-work-function materials is governed by the O vacancy and O interstitial generation, respectively. From our theoretical considerations, we have found that the work-function pinning-free-region generally appears due to me difference in the mechanism of Fermi-level pinning of high- and low-work-function materials. Further, we also discuss the interface physics between pure metal gates and high-k dielectrics.
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U2 - 10.1109/ICSICT.2006.306258
DO - 10.1109/ICSICT.2006.306258
M3 - Conference contribution
AN - SCOPUS:34547243031
SN - 1424401615
SN - 9781424401611
T3 - ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
SP - 384
EP - 387
BT - ICSICT-2006
PB - IEEE Computer Society
T2 - ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
Y2 - 23 October 2006 through 26 October 2006
ER -