Physics of interfaces between gate electrodes and high-k dielectrics

K. Shiraishi; H. Takeuchi; Y. Akasaka; T. Nakayama; S. Miyazaki; T. Nakaoka; A. Ohta; H. Watanabe; N. Umezawa; K. Ohmori; P. Ahmet; K. Toii; T. Chikyow; Y. Nara; T. J.King Liu; H. Iwai; K. Yamada

doi:10.1109/ICSICT.2006.306258

Physics of interfaces between gate electrodes and high-k dielectrics

K. Shiraishi, H. Takeuchi, Y. Akasaka, T. Nakayama, S. Miyazaki, T. Nakaoka, A. Ohta, H. Watanabe, N. Umezawa, K. Ohmori, P. Ahmet, K. Toii, T. Chikyow, Y. Nara, T. J.King Liu, H. Iwai, K. Yamada

Advanced Institute for Materials Research (AIMR)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high- and low-work-function materials is governed by the O vacancy and O interstitial generation, respectively. From our theoretical considerations, we have found that the work-function pinning-free-region generally appears due to me difference in the mechanism of Fermi-level pinning of high- and low-work-function materials. Further, we also discuss the interface physics between pure metal gates and high-k dielectrics.

Original language	English
Title of host publication	ICSICT-2006
Subtitle of host publication	2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Publisher	IEEE Computer Society
Pages	384-387
Number of pages	4
ISBN (Print)	1424401615, 9781424401611
DOIs	https://doi.org/10.1109/ICSICT.2006.306258
Publication status	Published - 2006
Event	ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China Duration: 2006 Oct 23 → 2006 Oct 26

Publication series

Name	ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

Other	ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
Country	China
City	Shanghai
Period	06/10/23 → 06/10/26

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/ICSICT.2006.306258

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Shiraishi, K., Takeuchi, H., Akasaka, Y., Nakayama, T., Miyazaki, S., Nakaoka, T., Ohta, A., Watanabe, H., Umezawa, N., Ohmori, K., Ahmet, P., Toii, K., Chikyow, T., Nara, Y., Liu, T. J. K., Iwai, H., & Yamada, K. (2006). Physics of interfaces between gate electrodes and high-k dielectrics. In ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 384-387). [4098115] (ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). IEEE Computer Society. https://doi.org/10.1109/ICSICT.2006.306258

Physics of interfaces between gate electrodes and high-k dielectrics. / Shiraishi, K.; Takeuchi, H.; Akasaka, Y.; Nakayama, T.; Miyazaki, S.; Nakaoka, T.; Ohta, A.; Watanabe, H.; Umezawa, N.; Ohmori, K.; Ahmet, P.; Toii, K.; Chikyow, T.; Nara, Y.; Liu, T. J.King; Iwai, H.; Yamada, K.

ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. IEEE Computer Society, 2006. p. 384-387 4098115 (ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Shiraishi, K, Takeuchi, H, Akasaka, Y, Nakayama, T, Miyazaki, S, Nakaoka, T, Ohta, A, Watanabe, H, Umezawa, N, Ohmori, K, Ahmet, P, Toii, K, Chikyow, T, Nara, Y, Liu, TJK, Iwai, H & Yamada, K 2006, Physics of interfaces between gate electrodes and high-k dielectrics. in ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 4098115, ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, IEEE Computer Society, pp. 384-387, ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 06/10/23. https://doi.org/10.1109/ICSICT.2006.306258

Shiraishi K, Takeuchi H, Akasaka Y, Nakayama T, Miyazaki S, Nakaoka T et al. Physics of interfaces between gate electrodes and high-k dielectrics. In ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. IEEE Computer Society. 2006. p. 384-387. 4098115. (ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings). https://doi.org/10.1109/ICSICT.2006.306258

Shiraishi, K. ; Takeuchi, H. ; Akasaka, Y. ; Nakayama, T. ; Miyazaki, S. ; Nakaoka, T. ; Ohta, A. ; Watanabe, H. ; Umezawa, N. ; Ohmori, K. ; Ahmet, P. ; Toii, K. ; Chikyow, T. ; Nara, Y. ; Liu, T. J.King ; Iwai, H. ; Yamada, K. / Physics of interfaces between gate electrodes and high-k dielectrics. ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. IEEE Computer Society, 2006. pp. 384-387 (ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings).

@inproceedings{ea8dc8fdb6754e0fa63bc477f8f69fa9,

title = "Physics of interfaces between gate electrodes and high-k dielectrics",

abstract = "Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high- and low-work-function materials is governed by the O vacancy and O interstitial generation, respectively. From our theoretical considerations, we have found that the work-function pinning-free-region generally appears due to me difference in the mechanism of Fermi-level pinning of high- and low-work-function materials. Further, we also discuss the interface physics between pure metal gates and high-k dielectrics.",

author = "K. Shiraishi and H. Takeuchi and Y. Akasaka and T. Nakayama and S. Miyazaki and T. Nakaoka and A. Ohta and H. Watanabe and N. Umezawa and K. Ohmori and P. Ahmet and K. Toii and T. Chikyow and Y. Nara and Liu, {T. J.King} and H. Iwai and K. Yamada",

year = "2006",

doi = "10.1109/ICSICT.2006.306258",

language = "English",

isbn = "1424401615",

series = "ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings",

publisher = "IEEE Computer Society",

pages = "384--387",

booktitle = "ICSICT-2006",

note = "ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology ; Conference date: 23-10-2006 Through 26-10-2006",

}

TY - GEN

T1 - Physics of interfaces between gate electrodes and high-k dielectrics

AU - Shiraishi, K.

AU - Takeuchi, H.

AU - Akasaka, Y.

AU - Nakayama, T.

AU - Miyazaki, S.

AU - Nakaoka, T.

AU - Ohta, A.

AU - Watanabe, H.

AU - Umezawa, N.

AU - Ohmori, K.

AU - Ahmet, P.

AU - Toii, K.

AU - Chikyow, T.

AU - Nara, Y.

AU - Liu, T. J.King

AU - Iwai, H.

AU - Yamada, K.

PY - 2006

Y1 - 2006

N2 - Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high- and low-work-function materials is governed by the O vacancy and O interstitial generation, respectively. From our theoretical considerations, we have found that the work-function pinning-free-region generally appears due to me difference in the mechanism of Fermi-level pinning of high- and low-work-function materials. Further, we also discuss the interface physics between pure metal gates and high-k dielectrics.

AB - Fermi-level pinning of poly-Si and metal-silicide gate materials on Hf-based gate dielectrics has been systematically studied theoretically. Fermi-level pinning in high- and low-work-function materials is governed by the O vacancy and O interstitial generation, respectively. From our theoretical considerations, we have found that the work-function pinning-free-region generally appears due to me difference in the mechanism of Fermi-level pinning of high- and low-work-function materials. Further, we also discuss the interface physics between pure metal gates and high-k dielectrics.

UR - http://www.scopus.com/inward/record.url?scp=34547243031&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547243031&partnerID=8YFLogxK

U2 - 10.1109/ICSICT.2006.306258

DO - 10.1109/ICSICT.2006.306258

M3 - Conference contribution

AN - SCOPUS:34547243031

SN - 1424401615

SN - 9781424401611

T3 - ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

SP - 384

EP - 387

BT - ICSICT-2006

PB - IEEE Computer Society

T2 - ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology

Y2 - 23 October 2006 through 26 October 2006

ER -