This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, using PC material with the lowest RESET current. We discuss the margins for RESET/SET/READ operations based on measurement results and identified that it is impossible to distinguish between RESET/SET operations by controlling the bitline voltage. We propose a new tri-level voltage word-line control (3LV-WL) scheme to clearly operate SET operations. Moreover, we investigated the READ disturb operation and developed a new reduced-actual-READ-access (RA2) scheme to attain 500 times the READ retention time. We also developed a source line control (SLC) scheme to attain an 18% smaller cell size and a 19-F2 memory cell with enough RESET current to clearly reset the PC material. With the application of these approaches, we established RESET/SET/READ operations with the lowest possible voltage, 1.5 V with logic CMOS, for a low-cost embedded memory with a few additional masks.