Phase change RAM operated with 1.5-V CMOS as low cost embedded memory

K. Osada, T. Kawahara, R. Takemura, N. Kitai, N. Takaura, N. Matsuzaki, K. Kurotsuchi, H. Moriya, M. Moniwa

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    15 Citations (Scopus)


    This paper describes a phase change (PC) RAM operated at the lowest possible voltage, 1.5 V, with a CMOS memory array, using PC material with the lowest RESET current. We discuss the margins for RESET/SET/READ operations based on measurement results and identified that it is impossible to distinguish between RESET/SET operations by controlling the bitline voltage. We propose a new tri-level voltage word-line control (3LV-WL) scheme to clearly operate SET operations. Moreover, we investigated the READ disturb operation and developed a new reduced-actual-READ-access (RA2) scheme to attain 500 times the READ retention time. We also developed a source line control (SLC) scheme to attain an 18% smaller cell size and a 19-F2 memory cell with enough RESET current to clearly reset the PC material. With the application of these approaches, we established RESET/SET/READ operations with the lowest possible voltage, 1.5 V with logic CMOS, for a low-cost embedded memory with a few additional masks.

    Original languageEnglish
    Title of host publicationProceedings of the IEEE 2005 Custom Integrated Circuits Conference
    PublisherInstitute of Electrical and Electronics Engineers Inc.
    Number of pages4
    ISBN (Print)0780390237, 9780780390232
    Publication statusPublished - 2005
    EventIEEE 2005 Custom Integrated Circuits Conference - San Jose, CA, United States
    Duration: 2005 Sep 182005 Sep 21

    Publication series

    NameProceedings of the Custom Integrated Circuits Conference
    ISSN (Print)0886-5930


    OtherIEEE 2005 Custom Integrated Circuits Conference
    Country/TerritoryUnited States
    CitySan Jose, CA

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering


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