Performance tuning and analysis of future vector processors based on the roofline model

Yoshiei Sato, Ryuichi Nagaoka, Akihiro Musa, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

Because of a recent steep drop in the ratio of memory bandwidth to computational performance (B/F) of vector processors, their advantage against scalar ones regarding relatively high sustained performance is decaying. To cover the insufficient B/F rate, an on-chip vector cache mechanism is promising for the vector processors. Although the effectiveness of the vector cache has been evaluated, cache-conscious tuning of vector codes and the analysis of the obtained performance have not been discussed yet. Under this situation, the purpose of this paper is to establish a strategy for performance tuning of a vector processor with a cache to exploit its potential. To analyze its sustained performance, this paper uses the roofline model. Several optimization techniques are applied to real scientific and engineering applications, and their effects are assessed with the model. We confirm that the model can guide users to effective tuning so as to maximize its gain. We also discuss the energy efficiency of the on-chip vector cache.

Original languageEnglish
Title of host publicationProceedings of the 10th MEDEA Workshop on MEmory Performance
Subtitle of host publicationDEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the PACT 2009 Conference
Pages7-14
Number of pages8
DOIs
Publication statusPublished - 2009 Dec 1
Event10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the Int. Conf. on Parallel Architectures and Compilation Techniques, PACT 2009 - Raleigh, NC, United States
Duration: 2009 Sep 132009 Sep 13

Publication series

NameACM International Conference Proceeding Series

Other

Other10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the Int. Conf. on Parallel Architectures and Compilation Techniques, PACT 2009
CountryUnited States
CityRaleigh, NC
Period09/9/1309/9/13

Keywords

  • Energy consumption
  • Memory system
  • Performance characterization
  • Performance model
  • Performance optimization
  • Scientific application
  • Vector cache
  • Vector processing

ASJC Scopus subject areas

  • Software
  • Human-Computer Interaction
  • Computer Vision and Pattern Recognition
  • Computer Networks and Communications

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