Performance tuning and analysis of future vector processors based on the roofline model

Yoshiei Sato; Ryuichi Nagaoka; Akihiro Musa; Ryusuke Egawa; Hiroyuki Takizawa; Koki Okabe; Hiroaki Kobayashi

doi:10.1145/1621960.1621962

Performance tuning and analysis of future vector processors based on the roofline model

Yoshiei Sato, Ryuichi Nagaoka, Akihiro Musa, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Citations (Scopus)

Abstract

Because of a recent steep drop in the ratio of memory bandwidth to computational performance (B/F) of vector processors, their advantage against scalar ones regarding relatively high sustained performance is decaying. To cover the insufficient B/F rate, an on-chip vector cache mechanism is promising for the vector processors. Although the effectiveness of the vector cache has been evaluated, cache-conscious tuning of vector codes and the analysis of the obtained performance have not been discussed yet. Under this situation, the purpose of this paper is to establish a strategy for performance tuning of a vector processor with a cache to exploit its potential. To analyze its sustained performance, this paper uses the roofline model. Several optimization techniques are applied to real scientific and engineering applications, and their effects are assessed with the model. We confirm that the model can guide users to effective tuning so as to maximize its gain. We also discuss the energy efficiency of the on-chip vector cache.

Original language	English
Title of host publication	Proceedings of the 10th MEDEA Workshop on MEmory Performance
Subtitle of host publication	DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the PACT 2009 Conference
Pages	7-14
Number of pages	8
DOIs	https://doi.org/10.1145/1621960.1621962
Publication status	Published - 2009 Dec 1
Event	10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the Int. Conf. on Parallel Architectures and Compilation Techniques, PACT 2009 - Raleigh, NC, United States Duration: 2009 Sep 13 → 2009 Sep 13

Publication series

Name	ACM International Conference Proceeding Series

Other

Other	10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the Int. Conf. on Parallel Architectures and Compilation Techniques, PACT 2009
Country/Territory	United States
City	Raleigh, NC
Period	09/9/13 → 09/9/13

Keywords

Energy consumption
Memory system
Performance characterization
Performance model
Performance optimization
Scientific application
Vector cache
Vector processing

ASJC Scopus subject areas

Software
Human-Computer Interaction
Computer Vision and Pattern Recognition
Computer Networks and Communications

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1145/1621960.1621962

Cite this

Sato, Y., Nagaoka, R., Musa, A., Egawa, R., Takizawa, H., Okabe, K., & Kobayashi, H. (2009). Performance tuning and analysis of future vector processors based on the roofline model. In Proceedings of the 10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the PACT 2009 Conference (pp. 7-14). (ACM International Conference Proceeding Series). https://doi.org/10.1145/1621960.1621962

Performance tuning and analysis of future vector processors based on the roofline model. / Sato, Yoshiei; Nagaoka, Ryuichi; Musa, Akihiro; Egawa, Ryusuke; Takizawa, Hiroyuki; Okabe, Koki; Kobayashi, Hiroaki.

Proceedings of the 10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the PACT 2009 Conference. 2009. p. 7-14 (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sato, Y, Nagaoka, R, Musa, A, Egawa, R, Takizawa, H, Okabe, K & Kobayashi, H 2009, Performance tuning and analysis of future vector processors based on the roofline model. in Proceedings of the 10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the PACT 2009 Conference. ACM International Conference Proceeding Series, pp. 7-14, 10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the Int. Conf. on Parallel Architectures and Compilation Techniques, PACT 2009, Raleigh, NC, United States, 09/9/13. https://doi.org/10.1145/1621960.1621962

Sato Y, Nagaoka R, Musa A, Egawa R, Takizawa H, Okabe K et al. Performance tuning and analysis of future vector processors based on the roofline model. In Proceedings of the 10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the PACT 2009 Conference. 2009. p. 7-14. (ACM International Conference Proceeding Series). https://doi.org/10.1145/1621960.1621962

Sato, Yoshiei ; Nagaoka, Ryuichi ; Musa, Akihiro ; Egawa, Ryusuke ; Takizawa, Hiroyuki ; Okabe, Koki ; Kobayashi, Hiroaki. / Performance tuning and analysis of future vector processors based on the roofline model. Proceedings of the 10th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '09, held in conjunction with the PACT 2009 Conference. 2009. pp. 7-14 (ACM International Conference Proceeding Series).

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AU - Musa, Akihiro

AU - Egawa, Ryusuke

AU - Takizawa, Hiroyuki

AU - Okabe, Koki

AU - Kobayashi, Hiroaki

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AB - Because of a recent steep drop in the ratio of memory bandwidth to computational performance (B/F) of vector processors, their advantage against scalar ones regarding relatively high sustained performance is decaying. To cover the insufficient B/F rate, an on-chip vector cache mechanism is promising for the vector processors. Although the effectiveness of the vector cache has been evaluated, cache-conscious tuning of vector codes and the analysis of the obtained performance have not been discussed yet. Under this situation, the purpose of this paper is to establish a strategy for performance tuning of a vector processor with a cache to exploit its potential. To analyze its sustained performance, this paper uses the roofline model. Several optimization techniques are applied to real scientific and engineering applications, and their effects are assessed with the model. We confirm that the model can guide users to effective tuning so as to maximize its gain. We also discuss the energy efficiency of the on-chip vector cache.

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Performance tuning and analysis of future vector processors based on the roofline model

Abstract

Publication series

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Keywords

ASJC Scopus subject areas

UN SDGs

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