Performance limit of parallel electric field tunnel FET and improvement by modified gate and channel configurations

Y. Morita, T. Mori, S. Migita, W. Mizubayashi, A. Tanabe, K. Fukuda, T. Matsukawa, Kazuhiko Endo, S. O'uchi, Y. X. Liu, M. Masahara, H. Ota

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

The performance of parallel electric field tunnel field-effect transistors (TFETs), in which band-to-band tunneling (BTBT) was initiated in-line to the gate electric field, was evaluated. The TFET was fabricated by inserting a parallel-plate tunnel capacitor between heavily doped source wells and gate insulators. Analysis using a distributed-element circuit model indicated there should be a limit of the drain current caused by the self-voltage-drop effect in the ultrathin channel layer. We also propose a scheme to improve the performance of the TFETs by modification of the gate and channel configurations.

Original languageEnglish
Title of host publicationESSDERC 2013 - Proceedings of the 43rd European Solid-State Device Research Conference
PublisherIEEE Computer Society
Pages45-48
Number of pages4
ISBN (Print)9781479906499
DOIs
Publication statusPublished - 2013 Jan 1
Externally publishedYes
Event43rd European Solid-State Device Research Conference, ESSDERC 2013 - Bucharest, Romania
Duration: 2013 Sep 162013 Sep 20

Publication series

NameEuropean Solid-State Device Research Conference
ISSN (Print)1930-8876

Conference

Conference43rd European Solid-State Device Research Conference, ESSDERC 2013
CountryRomania
CityBucharest
Period13/9/1613/9/20

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality

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