TY - GEN
T1 - Performance evaluation of a vector supercomputer SX-aurora TSUBASA
AU - Komatsu, Kazuhiko
AU - Momose, Shintaro
AU - Isobe, Yoko
AU - Watanabe, Osamu
AU - Musa, Akihiro
AU - Yokokawa, Mitsuo
AU - Aoyama, Toshikazu
AU - Sato, Masayuki
AU - Kobayashi, Hiroaki
N1 - Funding Information:
The authors would like to thank Hiroyuki Takizawa, Ryusuke Egawa, Yasuhisa Masaoka, and Souya Fujimoto for useful discussions. The authors also thank Association for Real-time Tsunami Science (ARTS) for use of the tsunami simulation code. The authors also thank the SX-Aurora TSUB-ASA beta program for early access to SX-Aurora TSUBASA. This research was partially supported by Grants-in-Aid for Scientific Research(S) #17H06108, Research(B) #16H02822, Research(C) #18K11322, Research(C) #18K11325, and Joint Usage/Research Center for Interdisciplinary Large-scale Information Infrastructures in Japan (Project ID: jh180040-NAH).
Publisher Copyright:
© 2018 IEEE.
PY - 2019/3/11
Y1 - 2019/3/11
N2 - A new SX-Aurora TSUBASA vector supercomputer has been released, and it features a new system architecture and a new execution model to achieve high sustained performance, especially for memory-intensive applications. In SX-Aurora TSUBASA, the vector host (VH) of a standard x86 Linux node is attached to the vector engine (VE) of the newly developed vector processor. An application is executed on the VE, and only system calls are offloaded to the VH. This new execution model can avoid redundant data transfers between the VH and VE that can easily become a bottleneck in the conventional execution model. This paper examines the potential of SX-Aurora TSUBASA. First, the basic performance is clarified by evaluating benchmark programs. Then, the effectiveness of the new execution model is examined by using a microbenchmark. Finally, the potential of SX-Aurora TSUBASA is clarified through evaluations of practical applications.
AB - A new SX-Aurora TSUBASA vector supercomputer has been released, and it features a new system architecture and a new execution model to achieve high sustained performance, especially for memory-intensive applications. In SX-Aurora TSUBASA, the vector host (VH) of a standard x86 Linux node is attached to the vector engine (VE) of the newly developed vector processor. An application is executed on the VE, and only system calls are offloaded to the VH. This new execution model can avoid redundant data transfers between the VH and VE that can easily become a bottleneck in the conventional execution model. This paper examines the potential of SX-Aurora TSUBASA. First, the basic performance is clarified by evaluating benchmark programs. Then, the effectiveness of the new execution model is examined by using a microbenchmark. Finally, the potential of SX-Aurora TSUBASA is clarified through evaluations of practical applications.
UR - http://www.scopus.com/inward/record.url?scp=85064110606&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85064110606&partnerID=8YFLogxK
U2 - 10.1109/SC.2018.00057
DO - 10.1109/SC.2018.00057
M3 - Conference contribution
AN - SCOPUS:85064110606
T3 - Proceedings - International Conference for High Performance Computing, Networking, Storage, and Analysis, SC 2018
SP - 685
EP - 696
BT - Proceedings - International Conference for High Performance Computing, Networking, Storage, and Analysis, SC 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2018 International Conference for High Performance Computing, Networking, Storage, and Analysis, SC 2018
Y2 - 11 November 2018 through 16 November 2018
ER -