Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem

Antoniette Mondigo, Kentaro Sano, Hirovuki Takizawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

To precisely evaluate the sustained performance and scalability of pipelined multiple FPGAs, this paper presents the implementation of a high-speed communication subsystem for a deeply pipelined stream computing platform. Internally, a pipeline of hardware modules for a domain-specific application is implemented in the FPGAs, where they are directly connected through their serial transceiver links. The necessary inter-FPGA communication subsystem with a flow control mechanism is implemented with Intel Arria 10 FPGAs, where the resource consumption and sustained network throughput are obtained, which averages at 7.92 GB/s. Performance estimation of a fluid simulation using the measured inter-FPGA network parameters is shown for a varied pipeline depth with explored temporal and spatial parallel options. Results show that the proposed platform with 16 FPGAs is estimated to achieve a sustained performance of 4.8 TFlops and may be scaled further by deepening the pipeline with even up to 128 FPGAs.

Original languageEnglish
Title of host publication2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781538674796
DOIs
Publication statusPublished - 2018 Aug 23
Event29th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2018 - Milan, Italy
Duration: 2018 Jul 102018 Jul 12

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Volume2018-July
ISSN (Print)1063-6862

Other

Other29th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2018
CountryItaly
CityMilan
Period18/7/1018/7/12

Keywords

  • communication
  • deep pipeline
  • flow control
  • multiple FPGAs
  • performance estimation
  • stream computing

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

Fingerprint Dive into the research topics of 'Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem'. Together they form a unique fingerprint.

  • Cite this

    Mondigo, A., Sano, K., & Takizawa, H. (2018). Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem. In 2018 IEEE 29th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2018 [8445100] (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2018-July). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASAP.2018.8445100