Performance boost using a new device structure design for SOI MOSFETs beyond 25nm node

W. Cheng, A. Teramoto, T. Ohmi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this study, we model the device performance in ultra short-channel inversion- and accumulation-mode SOI MOSFETs beyond the 25nm node. The performance is obviously improved in accumulation mode SOI MOSFETs while device downscaling. Furthermore, we reveal the device design guideline for the short-channel accumulation mode SOI MOSFETs.

Original languageEnglish
Title of host publicationECS Transactions - 5th International Symposium on ULSI Process Integration
Pages349-355
Number of pages7
Edition6
DOIs
Publication statusPublished - 2007 Dec 1
Event5th International Symposium on ULSI Process Integration - 212th ECS Meeting - Washington, DC, United States
Duration: 2007 Oct 72007 Oct 12

Publication series

NameECS Transactions
Number6
Volume11
ISSN (Print)1938-5862
ISSN (Electronic)1938-6737

Other

Other5th International Symposium on ULSI Process Integration - 212th ECS Meeting
CountryUnited States
CityWashington, DC
Period07/10/707/10/12

ASJC Scopus subject areas

  • Engineering(all)

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