Perceptron-based Cache Bypassing for Way-Adaptable Caches

Masayuki Sato, Yongcheng Chen, Haruya Kikuchi, Kazuhiko Komatsu, Hiroaki Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A way-adaptable cache, which adaptively activates/inactivates cache ways, has the potential to reduce the cache energy consumption. However, the cache activates a non-negligible number of ways to store dead blocks, which are not reused and do not contribute to performance improvement. Therefore, this paper proposes a perceptron-based cache bypassing mechanism for the way-adaptable cache to eliminate dead blocks. The evaluation results show that the proposed mechanism can reduce the cache energy consumption by up to 67%, and 14% on average.

Original languageEnglish
Title of host publicationIEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728117485
DOIs
Publication statusPublished - 2019 May 23
Event22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Yokohama, Japan
Duration: 2019 Apr 172019 Apr 19

Publication series

NameIEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019 - Proceedings

Conference

Conference22nd IEEE Symposium on Low-Power and High-Speed Chips and Systems, COOL CHIPS 2019
CountryJapan
CityYokohama
Period19/4/1719/4/19

Keywords

  • cache memory
  • energy consumption
  • perceptron reuse prediction
  • way-adaptable cache

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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