Parallel image processing field programmable gate array for real time image processing system

Takeaki Sugimura, Jeoungchill Shim, Hiroyuki Kurino, Mitsumasa Koyanagi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

A parallel image processing field programmable gate array (FPGA) for real time image processing system has been proposed to realize high image processing speed and flexibility. This FPGA has a small size configuration memory. In addition, a parallel reconfigurable interconnection network and logic blocks have been used in this FPGA. A test chip was designed and fabricated using 0.35μm CMOS technology. It was confirmed in the test chip that the reconfiguration of the image processing is successfully performed.

Original languageEnglish
Title of host publicationProceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages372-374
Number of pages3
ISBN (Electronic)0780383206, 9780780383203
DOIs
Publication statusPublished - 2003 Jan 1
Event2nd International Conference on Field Programmable Technology, FPT 2003 - Tokyo, Japan
Duration: 2003 Dec 152003 Dec 17

Publication series

NameProceedings - 2003 IEEE International Conference on Field-Programmable Technology, FPT 2003

Other

Other2nd International Conference on Field Programmable Technology, FPT 2003
CountryJapan
CityTokyo
Period03/12/1503/12/17

ASJC Scopus subject areas

  • Computer Science Applications
  • Software

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