Parallel evolutionary graph generation with terminal-color constraint and its application to current-mode logic circuit design

Masanori Natsui; Takafumi Aoki; Tatsuo Higuchi

Parallel evolutionary graph generation with terminal-color constraint and its application to current-mode logic circuit design

Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi

Research output: Contribution to journal › Article › peer-review

Abstract

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG) and its extension to a parallel version. A new version of parallel EGG system is based on a coarse-grained model of parallel processing and can synthesize heterogeneous networks of various different components efficiently. The potential capability of parallel EGG system is demonstrated through the design of current-mode logic circuits.

Original language	English
Pages (from-to)	2061-2071
Number of pages	11
Journal	IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Volume	E85-A
Issue number	9
Publication status	Published - 2002 Sep

Keywords

Arithmetic circuits
Evolutionary computation
Genetic algorithms
Multiple-valued logic

ASJC Scopus subject areas

Signal Processing
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering
Applied Mathematics

Cite this

Parallel evolutionary graph generation with terminal-color constraint and its application to current-mode logic circuit design. / Natsui, Masanori ; Aoki, Takafumi; Higuchi, Tatsuo.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E85-A, No. 9, 09.2002, p. 2061-2071.

Research output: Contribution to journal › Article › peer-review

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Parallel evolutionary graph generation with terminal-color constraint and its application to current-mode logic circuit design

Abstract

Keywords

ASJC Scopus subject areas

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