Parallel evolutionary graph generation with terminal-color constraint and its application to current-mode logic circuit design

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG) and its extension to a parallel version. A new version of parallel EGG system is based on a coarse-grained model of parallel processing and can synthesize heterogeneous networks of various different components efficiently. The potential capability of parallel EGG system is demonstrated through the design of current-mode logic circuits.

Original languageEnglish
Pages (from-to)2061-2071
Number of pages11
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE85-A
Issue number9
Publication statusPublished - 2002 Sep

Keywords

  • Arithmetic circuits
  • Evolutionary computation
  • Genetic algorithms
  • Multiple-valued logic

ASJC Scopus subject areas

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

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