Parallel evolutionary graph generation on a PC cluster and its application to multiple-valued circuit synthesis

Research output: Contribution to journalConference article

1 Citation (Scopus)

Abstract

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG) and its extension to a parallel version. The parallel EGG system presented in this paper is based on a coarse-grained model of parallel processing and is implemented on a 16-node Linux PC cluster. The potential capability of parallel EGG system is demonstrated through the synthesis of a radix-4 Signed-Digit (SD) full adder circuit.

Original languageEnglish
Pages (from-to)96-102
Number of pages7
JournalProceedings of The International Symposium on Multiple-Valued Logic
Publication statusPublished - 2002 Jan 1
Event32nd IEEE International Symposium on Multiple-Valued Logic - Boston, MA, United States
Duration: 2002 May 152002 May 18

ASJC Scopus subject areas

  • Computer Science(all)
  • Mathematics(all)

Fingerprint Dive into the research topics of 'Parallel evolutionary graph generation on a PC cluster and its application to multiple-valued circuit synthesis'. Together they form a unique fingerprint.

  • Cite this