Abstract
This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG) and its extension to a parallel version. The parallel EGG system presented in this paper is based on a coarse-grained model of parallel processing and is implemented on a 16-node Linux PC cluster. The potential capability of parallel EGG system is demonstrated through the synthesis of a radix-4 Signed-Digit (SD) full adder circuit.
Original language | English |
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Pages (from-to) | 96-102 |
Number of pages | 7 |
Journal | Proceedings of The International Symposium on Multiple-Valued Logic |
Publication status | Published - 2002 Jan 1 |
Event | 32nd IEEE International Symposium on Multiple-Valued Logic - Boston, MA, United States Duration: 2002 May 15 → 2002 May 18 |
ASJC Scopus subject areas
- Computer Science(all)
- Mathematics(all)