Optimum design of conversion gain and full well capacity in CMOS image sensor with lateral overflow integration capacitor

Nana Akahane, Satoru Adachi, Koichi Mizobuchi, Shigetoshi Sugawa

Research output: Contribution to journalArticlepeer-review

19 Citations (Scopus)

Abstract

An optimum design theory to clarify a possible limit of achieving both high conversion gain (CG) and full well capacity (FWC) at the same time in a CMOS image sensor with a lateral overflow integration capacitor (LOFIC) in a pixel is discussed. The possible limit of both high CG and high FWC is theoretically derived from a signal-to-noise-ratio (SNR) formula at a switching point from a low light signal (S1) to a bright one (S2). Based on this theory, a 1/4-in VGA-format 5.6-μ-pixel-pitch CMOS image sensor has been fabricated through a 0.18-μm 2P3M CMOS technology. A high-quality wide-dynamic-range image sensing has been demonstrated with no significant visible noise, achieving over 32 dB of SNR for an 18% gray card.

Original languageEnglish
Pages (from-to)2429-2435
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume56
Issue number11
DOIs
Publication statusPublished - 2009

Keywords

  • CMOS image sensor
  • Conversion gain (CG)
  • Full well capacity (FWC)
  • Signal-to-noise ratio (SNR)

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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