In this paper, the model for wire length distribution model in three dimensional LSI is derived using Rent's rule. The number of the vertical interconnections and the ratio in all of wirings can be calculated with this model. This model clearly shows that many vertical interconnections are effectively utilized in chips with high Rent's constant p. We also evaluate the vertical interconnection density and the occupied area by the vertical interconnection in a chip.
ASJC Scopus subject areas
- Chemical Engineering(all)