Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors

A. Rothschild, R. Mitsuhashi, C. Kerner, X. Shi, J. L. Everaert, L. Date, T. Conard, O. Richard, C. Vrancken, R. Verbeeck, A. Veloso, A. Lauwers, M. De Potter, I. Debusschere, M. Jurczak, M. Niwa, P. Absil, S. Biesemans

Research output: Contribution to journalArticlepeer-review

3 Citations (Scopus)


We report for the first time that the optimization of a HfSiON process on Ni-FUSI devices is best tackled using a design of experiments (DOE [Myers RH, Montgomery. Response surface methodology. New York, DC: Wiley; 1995]) approach. We show that a DOE allows for directly linking process parameters to relevant short channel performance metrics. By tuning the SiO2 thickness, HfSiO thickness, Hf concentration, nitridation parameters and by using response surface modeling (RSM), we report an improvement of 12%/17% in nMOS/pMOS drive current (Idsat 600/255 uA/μm at Ioff = 20 pA/μm and Vdd = 1.1 V) over our reference process. In parallel, we demonstrate that by selecting the right parameters, plasma nitridation can outperform thermal nitridation with NH3. We believe that this new approach will be useful for device engineers and can be easily applied.

Original languageEnglish
Pages (from-to)521-524
Number of pages4
JournalMicroelectronics Reliability
Issue number4-5 SPEC. ISS.
Publication statusPublished - 2007 Apr
Externally publishedYes

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Safety, Risk, Reliability and Quality
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering


Dive into the research topics of 'Optimization of HfSiON using a design of experiment (DOE) approach on 0.45 V Vt Ni-FUSI CMOS transistors'. Together they form a unique fingerprint.

Cite this