Optimal periodical memory allocation for logic-in-memory image processors

Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

One major issue in designing image processors is to design a memory system that supports parallel access with a simple interconnection network. This paper presents a design methodology for a logic-in-memory architecture where each of memory modules is connected to its dedicated processing element(PE). An efficient memory allocation to minimize the number of memory modules and PEs under a time constraint is proposed based on regularity.

Original languageEnglish
Title of host publicationProceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Pages193-198
Number of pages6
DOIs
Publication statusPublished - 2006 Oct 9
EventIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006 - Klarlsruhe, Germany
Duration: 2006 Mar 22006 Mar 3

Publication series

NameProceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
Volume2006

Other

OtherIEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006
CountryGermany
CityKlarlsruhe
Period06/3/206/3/3

ASJC Scopus subject areas

  • Engineering(all)

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