Optimal integration and characteristics of vertical array devices for ultra-high density, bit-cost scalable flash memory

Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kido, Mitsuru Sato, Hiroyasu Tanaka, Yuzo Nagata, Yasuyuki Matsuoka, Yoshihisa Iwata, Hideaki Aochi, Akihiro Nitayama

Research output: Contribution to journalConference article

149 Citations (Scopus)

Abstract

Optimal process integration for array devices of Bit-Cost Scalable (BiCS) flash memory is successfully developed. We adopt SiN-based gate dielectrics for the consistency with the 'gate-first' process which is unique to BiCS flash technology, and 'macaroni' body FETs for better controllability over the sub-threshold characteristics of depletion-mode poly-silicon transistors. With these technologies and newly devised 4F2 cell array, BiCS flash becomes a promising candidate for future ultra-high density memory.

Original languageEnglish
Article number4418970
Pages (from-to)449-452
Number of pages4
JournalTechnical Digest - International Electron Devices Meeting, IEDM
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 IEEE International Electron Devices Meeting, IEDM - Washington, DC, United States
Duration: 2007 Dec 102007 Dec 12

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering
  • Materials Chemistry

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    Fukuzumi, Y., Katsumata, R., Kito, M., Kido, M., Sato, M., Tanaka, H., Nagata, Y., Matsuoka, Y., Iwata, Y., Aochi, H., & Nitayama, A. (2007). Optimal integration and characteristics of vertical array devices for ultra-high density, bit-cost scalable flash memory. Technical Digest - International Electron Devices Meeting, IEDM, 449-452. [4418970]. https://doi.org/10.1109/IEDM.2007.4418970