Optimal design of a VLSI processor with spatially and temporally parallel structure

Michitaka Kameyama, Masayuki Sasaki

Research output: Contribution to journalArticlepeer-review

Abstract

In intelligent integrated systems such as robotics for autonomous work, it is essential to respond to changes of the environment very quickly. Therefore, the development of special-purpose VLSI processors with minimum delay time becomes a very important subject. A suitable combination of spatially parallel and temporally parallel processing is very important to realize the minimum delay time. In this article, we present a scheduling algorithm for high-level synthesis, where the input to the scheduler is a behavioral description viewed as a data flow graph. The scheduler minimizes the delay time under the constraint of a silicon area and I/O pins.

Keywords

  • Intelligent integrated systems
  • Minimum delay time
  • Scheduling
  • Spatially parallel processing
  • Temporally parallel processing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Optimal design of a VLSI processor with spatially and temporally parallel structure'. Together they form a unique fingerprint.

Cite this