One-transistor-cell multiple-valued CAM for a collision detection VLSI processor

Takahiro Hanyu, Naoki Kanagawa, Michitaka Kameyama

Research output: Contribution to journalConference articlepeer-review

6 Citations (Scopus)


A content-addressable memory (CAM) based on multiple-valued logic is proposed for high-speed word-parallel magnitude comparison. The use of multiple-valued logic decreases the number of CAM cells in comparison with that of a corresponding binary one. This property not only reduces chip area, but also performs high-speed digit-serial search by iterative one-digit comparison. The function in the CAM consists of two basic components: a threshold operation and a logic-value conversion. Several complicated search operations are performed by the combination of these two basic functions.

Original languageEnglish
Pages (from-to)264-265
Number of pages2
JournalDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Publication statusPublished - 1996 Feb 1
EventProceedings of the 1996 IEEE International Solid-State Circuits Conference - San Francisco, CA, USA
Duration: 1996 Feb 81996 Feb 10

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


Dive into the research topics of 'One-transistor-cell multiple-valued CAM for a collision detection VLSI processor'. Together they form a unique fingerprint.

Cite this