An appropriate sampling of devices and architectures for onboard TDMA (time division multiple access) equipment, burst modems, baseband switches, and SCPC (single channel per carrier) multicarrier demodulators from the present to the year 2000 is presented along with device technology development trends, in terms of minimizing onboard weight and power consumption. The results show that at the present time (equivalent to around the year 1990 for onboard use), onboard TDMA equipment with a clock rate of lower than 100 MHz can be reasonably realized by parallel-processed CMOS-on-bulk LSI, while for TDMA equipment with clock rates of higher than 100 MHz, bipolar devices are more appropriate. The boundary clock rate is not so rigid, and toward the year 2000, the boundary is expected to move up to about 200 MHz. Moreover, the authors project that around the year 2000, GaAs devices will be more widely used for onboard high-bit rate TDMA. It is shown that for carrier frequencies up to 2 GHz, modem implementation in monolithic microwave ICs is most suitable. Moreover, it is found that coherent demodulation will not entail a bit penalty in hardware size and power consumption, because of implementing carrier recovery circuits using ICs and LSIs.
|Number of pages||16|
|Journal||IEEE Journal on Selected Areas in Communications|
|Publication status||Published - 1987 May|
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering