Abstract
The authors propose a digital demodulator with soft decision capability for onboard application. A prototype demodulator LSI which handles a 64-kb/s SCPC channel has been fabricated by using CMOS masterslice technology for reduction of hardware and power consumption. The proposed LSI demodulator requires 4 K gates and consumes 75 mW of power. Experimental results show that a prototype QPSK/OQPSK demodulator LSI has satisfactory error probability performance in conjunction with R equals 1/2, K equals 4 convolutional encoding and Viterbi decoding.
| Original language | English |
|---|---|
| Pages (from-to) | 1803-1808 |
| Number of pages | 6 |
| Journal | Conference Record - International Conference on Communications |
| Publication status | Published - 1986 Dec 1 |
ASJC Scopus subject areas
- Computer Networks and Communications
- Electrical and Electronic Engineering