Thin-film polyimides were prepared by solvent-less vapor deposition polymerization (VDP) from pyromellitic dianhydride and 4,4′-oxydianiline at 200 °C for liner dielectric formation of vertical interconnects called through-silicon vias (TSVs) used in three-dimensionally stacked integrated circuit (3DICs). FTIR, synchrotron XPS, and TDS were employed for determining the imidization ratio, and in addition, the mechanical properties, coefficient of thermal expansion and Young's modulus, of the VDP polyimide were characterized on Si wafers. The VDP polyimide exhibited extremely high conformality, beyond 75%, toward high-aspect-ratio deep Si holes, compared with conventional SiO2 prepared by plasma-enhanced chemical vapor deposition. The adhesion between the VDP polyimide and Si wafer was enhanced by an Al-chelate promotor. Remarkably, the VDP polyimide TSV liner dielectrics showed much less thermomechanical stresses applied to the Si surrounding the TSVs than the plasma-chemical vapor deposition SiO2. The small keep-out zone is expected for scaling down highly reliable 3DICs for the upcoming real artificial intelligence society.
- keep-out zone (KOZ)
- vapor deposition polymerization
ASJC Scopus subject areas
- Physical and Theoretical Chemistry
- Materials Chemistry
- Polymers and Plastics