TY - GEN
T1 - On the gate-stack origin threshold voltage variability in scaled FinFETs and Multi-FinFETs
AU - Liu, Y. X.
AU - Endo, K.
AU - O'uchi, S.
AU - Kamei, T.
AU - Tsukad, J.
AU - Yamauchi, H.
AU - Ishikawa, Y.
AU - Hayashida, T.
AU - Sakamoto, K.
AU - Kawa, T. Matsu
AU - Ogura, A.
AU - Masahara, M.
PY - 2010/10/19
Y1 - 2010/10/19
N2 - The Vt variability in scaled FinFETs with gate length (L g) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., workfunction variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching contribute to, not only the reduction of fin thickness (TSi) fluctuations, but also the reduction of gate-stack origin VTV. Moreover, it was experimentally found that the Vt of multi-FinFETs with the same gate area reduces with increasing the number of fins.
AB - The Vt variability in scaled FinFETs with gate length (L g) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., workfunction variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching contribute to, not only the reduction of fin thickness (TSi) fluctuations, but also the reduction of gate-stack origin VTV. Moreover, it was experimentally found that the Vt of multi-FinFETs with the same gate area reduces with increasing the number of fins.
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U2 - 10.1109/VLSIT.2010.5556187
DO - 10.1109/VLSIT.2010.5556187
M3 - Conference contribution
AN - SCOPUS:77957858500
SN - 9781424476374
T3 - Digest of Technical Papers - Symposium on VLSI Technology
SP - 101
EP - 102
BT - 2010 Symposium on VLSI Technology, VLSIT 2010
T2 - 2010 Symposium on VLSI Technology, VLSIT 2010
Y2 - 15 June 2010 through 17 June 2010
ER -