On the gate-stack origin threshold voltage variability in scaled FinFETs and Multi-FinFETs

Y. X. Liu; K. Endo; S. O'uchi; T. Kamei; J. Tsukad; H. Yamauchi; Y. Ishikawa; T. Hayashida; K. Sakamoto; T. Matsu Kawa; A. Ogura; M. Masahara

doi:10.1109/VLSIT.2010.5556187

On the gate-stack origin threshold voltage variability in scaled FinFETs and Multi-FinFETs

Y. X. Liu, K. Endo, S. O'uchi, T. Kamei, J. Tsukad, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, T. Matsu Kawa, A. Ogura, M. Masahara

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

40 Citations (Scopus)

Abstract

The V_t variability in scaled FinFETs with gate length (L _g) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (T_ox) dependence of Vt variation (VTV), the gate-stack origin, i.e., workfunction variation (WFV) and gate oxide charge (Q_ox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching contribute to, not only the reduction of fin thickness (T_Si) fluctuations, but also the reduction of gate-stack origin VTV. Moreover, it was experimentally found that the V_t of multi-FinFETs with the same gate area reduces with increasing the number of fins.

Original language	English
Title of host publication	2010 Symposium on VLSI Technology, VLSIT 2010
Pages	101-102
Number of pages	2
DOIs	https://doi.org/10.1109/VLSIT.2010.5556187
Publication status	Published - 2010 Oct 19
Externally published	Yes
Event	2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States Duration: 2010 Jun 15 → 2010 Jun 17

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)	0743-1562

Other

Other	2010 Symposium on VLSI Technology, VLSIT 2010
Country/Territory	United States
City	Honolulu, HI
Period	10/6/15 → 10/6/17

ASJC Scopus subject areas

Electrical and Electronic Engineering

Access to Document

10.1109/VLSIT.2010.5556187

Cite this

Liu, Y. X., Endo, K., O'uchi, S., Kamei, T., Tsukad, J., Yamauchi, H., Ishikawa, Y., Hayashida, T., Sakamoto, K., Kawa, T. M., Ogura, A., & Masahara, M. (2010). On the gate-stack origin threshold voltage variability in scaled FinFETs and Multi-FinFETs. In 2010 Symposium on VLSI Technology, VLSIT 2010 (pp. 101-102). [5556187] (Digest of Technical Papers - Symposium on VLSI Technology). https://doi.org/10.1109/VLSIT.2010.5556187

On the gate-stack origin threshold voltage variability in scaled FinFETs and Multi-FinFETs. / Liu, Y. X.; Endo, K.; O'uchi, S.; Kamei, T.; Tsukad, J.; Yamauchi, H.; Ishikawa, Y.; Hayashida, T.; Sakamoto, K.; Kawa, T. Matsu; Ogura, A.; Masahara, M.

2010 Symposium on VLSI Technology, VLSIT 2010. 2010. p. 101-102 5556187 (Digest of Technical Papers - Symposium on VLSI Technology).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Liu, YX, Endo, K, O'uchi, S, Kamei, T, Tsukad, J, Yamauchi, H, Ishikawa, Y, Hayashida, T, Sakamoto, K, Kawa, TM, Ogura, A & Masahara, M 2010, On the gate-stack origin threshold voltage variability in scaled FinFETs and Multi-FinFETs. in 2010 Symposium on VLSI Technology, VLSIT 2010., 5556187, Digest of Technical Papers - Symposium on VLSI Technology, pp. 101-102, 2010 Symposium on VLSI Technology, VLSIT 2010, Honolulu, HI, United States, 10/6/15. https://doi.org/10.1109/VLSIT.2010.5556187

Liu, Y. X. ; Endo, K. ; O'uchi, S. ; Kamei, T. ; Tsukad, J. ; Yamauchi, H. ; Ishikawa, Y. ; Hayashida, T. ; Sakamoto, K. ; Kawa, T. Matsu ; Ogura, A. ; Masahara, M. / On the gate-stack origin threshold voltage variability in scaled FinFETs and Multi-FinFETs. 2010 Symposium on VLSI Technology, VLSIT 2010. 2010. pp. 101-102 (Digest of Technical Papers - Symposium on VLSI Technology).

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abstract = "The Vt variability in scaled FinFETs with gate length (L g) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., workfunction variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching contribute to, not only the reduction of fin thickness (TSi) fluctuations, but also the reduction of gate-stack origin VTV. Moreover, it was experimentally found that the Vt of multi-FinFETs with the same gate area reduces with increasing the number of fins.",

author = "Liu, {Y. X.} and K. Endo and S. O'uchi and T. Kamei and J. Tsukad and H. Yamauchi and Y. Ishikawa and T. Hayashida and K. Sakamoto and Kawa, {T. Matsu} and A. Ogura and M. Masahara",

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AU - Liu, Y. X.

AU - Endo, K.

AU - O'uchi, S.

AU - Kamei, T.

AU - Tsukad, J.

AU - Yamauchi, H.

AU - Ishikawa, Y.

AU - Hayashida, T.

AU - Sakamoto, K.

AU - Kawa, T. Matsu

AU - Ogura, A.

AU - Masahara, M.

PY - 2010/10/19

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N2 - The Vt variability in scaled FinFETs with gate length (L g) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., workfunction variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching contribute to, not only the reduction of fin thickness (TSi) fluctuations, but also the reduction of gate-stack origin VTV. Moreover, it was experimentally found that the Vt of multi-FinFETs with the same gate area reduces with increasing the number of fins.

AB - The Vt variability in scaled FinFETs with gate length (L g) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., workfunction variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching contribute to, not only the reduction of fin thickness (TSi) fluctuations, but also the reduction of gate-stack origin VTV. Moreover, it was experimentally found that the Vt of multi-FinFETs with the same gate area reduces with increasing the number of fins.

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On the gate-stack origin threshold voltage variability in scaled FinFETs and Multi-FinFETs

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