On the gate-stack origin threshold voltage variability in scaled FinFETs and Multi-FinFETs

Y. X. Liu, K. Endo, S. O'uchi, T. Kamei, J. Tsukad, H. Yamauchi, Y. Ishikawa, T. Hayashida, K. Sakamoto, T. Matsu Kawa, A. Ogura, M. Masahara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

39 Citations (Scopus)

Abstract

The Vt variability in scaled FinFETs with gate length (L g) down to 25 nm was systematically investigated, for the first time. By investigating the gate oxide thickness (Tox) dependence of Vt variation (VTV), the gate-stack origin, i.e., workfunction variation (WFV) and gate oxide charge (Qox) variation (OCV) origin VTV were successfully separated. It was found that the atomically flat Si-fin sidewall channels fabricated by using the orientation dependent wet etching contribute to, not only the reduction of fin thickness (TSi) fluctuations, but also the reduction of gate-stack origin VTV. Moreover, it was experimentally found that the Vt of multi-FinFETs with the same gate area reduces with increasing the number of fins.

Original languageEnglish
Title of host publication2010 Symposium on VLSI Technology, VLSIT 2010
Pages101-102
Number of pages2
DOIs
Publication statusPublished - 2010 Oct 19
Externally publishedYes
Event2010 Symposium on VLSI Technology, VLSIT 2010 - Honolulu, HI, United States
Duration: 2010 Jun 152010 Jun 17

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
ISSN (Print)0743-1562

Other

Other2010 Symposium on VLSI Technology, VLSIT 2010
CountryUnited States
CityHonolulu, HI
Period10/6/1510/6/17

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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