On-chip hardware accelerator for model-based 3-D instrumentation using run-length matching

Masahiro Kamoshida, Takahiro Hanyu, Michitaka Kameyama

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper presents a hardware accelerator for the high-speed model-based 3-D instrumentation whose operations are primarily occupied by the matching between an input and a projected model images. Since each 3-D reference model is represented by polygons, memory capacity for the storage of models is greatly reduced. Moreover, a new matching scheme using a run-length encoding is introduced for precise a run-length encoding is introduced for precise data representation with smaller memory capacity. In the hardware implementation, run-length matching is simply performed by magnitude comparisons and subtractions, it is suitable for VLSI implementation. In the proposed accelerator for high-speed run-length matching, the matching operation is performed in parallel line by line, while one-line run-length matching is performed serially. The architecture using bit-serial processing elements (PEs) can achieve ideal parallelism of run-length matching with less hardware overhead than that using bit-parallel PEs. It is demonstrated that the processing speed of the proposed hardware is about 12 times faster than that of the corresponding hardware using bit-parallel PEs.

Original languageEnglish
Pages1319-1323
Number of pages5
Publication statusPublished - 1995 Dec 1
EventProceedings of the 1995 IEEE 21st International Conference on Industrial Electronics, Control, and Instrumentation. Part 1 (of 2) - Orlando, FL, USA
Duration: 1995 Nov 61995 Nov 10

Other

OtherProceedings of the 1995 IEEE 21st International Conference on Industrial Electronics, Control, and Instrumentation. Part 1 (of 2)
CityOrlando, FL, USA
Period95/11/695/11/10

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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