NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

Tohru Miwa; Junichi Yamada; Hiroki Koike; Hideo Toyoshima; Kazushi Amanuma; Sota Kobayashi; Toru Tatsumi; Yukihiro Maejima; Hiromitsu Hada; Takemitsu Kunio

NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

Tohru Miwa, Junichi Yamada, Hiroki Koike, Hideo Toyoshima, Kazushi Amanuma, Sota Kobayashi, Toru Tatsumi, Yukihiro Maejima, Hiromitsu Hada, Takemitsu Kunio

Research output: Contribution to journal › Conference article › peer-review

4 Citations (Scopus)

Abstract

This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell are overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.

Original language	English
Pages (from-to)	65-68
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
Publication status	Published - 2000 Jan 1
Externally published	Yes
Event	CICC 2000: 22nd Annual Custom Integrated Circuits Conference - Orlando, FL, USA Duration: 2000 May 21 → 2000 May 24

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors",

abstract = "This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell are overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.",

author = "Tohru Miwa and Junichi Yamada and Hiroki Koike and Hideo Toyoshima and Kazushi Amanuma and Sota Kobayashi and Toru Tatsumi and Yukihiro Maejima and Hiromitsu Hada and Takemitsu Kunio",

year = "2000",

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language = "English",

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journal = "Proceedings of the Custom Integrated Circuits Conference",

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T2 - CICC 2000: 22nd Annual Custom Integrated Circuits Conference

AU - Miwa, Tohru

AU - Yamada, Junichi

AU - Koike, Hiroki

AU - Toyoshima, Hideo

AU - Amanuma, Kazushi

AU - Kobayashi, Sota

AU - Tatsumi, Toru

AU - Maejima, Yukihiro

AU - Hada, Hiromitsu

AU - Kunio, Takemitsu

PY - 2000/1/1

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N2 - This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell are overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.

AB - This paper demonstrates new circuit technologies that enable a 0.25-μm ASIC SRAM macro to be nonvolatile with only a 17% cell are overhead (NV-SRAM: nonvolatile SRAM). New capacitor-on-metal/via-stacked-plug process technologies make it possible for a NV-SRAM cell to consist of a six-transistor ASIC SRAM cell and two back-up ferroelectric capacitors stacked over the SRAM portion. A Vdd/2 plate line architecture makes read/write fatigue virtually negligible. A 512-byte test chip has been successfully fabricated to show compatibility with ASIC technologies.

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ER -

NV-SRAM: a nonvolatile SRAM with back-up ferroelectric capacitors

Abstract

ASJC Scopus subject areas

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