Novel ultrahigh-density flash memory with a stacked-surrounding gate transistor (S-SGT) structured cell

Tetsuo Endoh, Kazushi Kinoshita, Takuji Tanigami, Yoshihisa Wada, Kota Sato, Kazuya Yamada, Takashi Yokoyama, Noboru Takeuchi, Kenichi Tanaka, Nobuyoshi Awaya, Keizou Sakiyama, Fujio Masuoka

Research output: Contribution to journalArticlepeer-review

41 Citations (Scopus)

Abstract

In order to overcome the limitation of cell area of 4F2 per bit In conventional NAND Flash memory cells, stacked-surrounding gate transistor (S-SGT) structured cell is proposed. This newly structured cell achieves a cell area of 4F2 / N per bit, where N is the number of stacked memory cells in one silicon pillar, without using multibit per memory cell technology. The S-SGT structured cell consisting of two stacked memory cells in one silicon pillar achieves a cell area per bit of less than 50% of the smallest reported NAND structured cell. The novel S-SGT structured cells are fabricated by vertical self-aligned processes using a 0.2 μm design rule. The S-SGT structured cell can be programmed and erased by uniform injection and uniform emission of Fowler-Nordheim (F-N) tunneling electrons over the whole channel area of the memory cell, respectively, which is the same program and erase mechanism as in conventional NAND structured cell. This high performance S-SGT structured cell is applicable to high-density nonvolatile memories for 16 G/64 G bit Flash memories and beyond.

Original languageEnglish
Pages (from-to)945-951
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume50
Issue number4
DOIs
Publication statusPublished - 2003 Apr 1

Keywords

  • 3-D device
  • Flash memory
  • S-SGT
  • SGT

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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