Novel switch-block architecture using reconfigurable context memory for multi-context FPGAs

Weisheng Chong, Masanori Hariyama, Michitaka Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

Dynamically-programmable gate arrays (DPGAs) promise lower cost implementations than conventional FPGAs since they efficiently reuse limited hardware resources in time. One of typical DPGA architectures is a multi-context one. Multi-context FPGAs (MC-FPGAs) have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. The additional memory planes cause significant overhead in area and power consumption. Especially, switch blocks require a much larger memory capacity than look-up tables. This paper proposes a novel switch block architecture that can greatly reduce the overhead of the context memory in MC-FPGAs. A fine-grained reconfigurable architecture for switch blocks is presented based on the fact that there are redundancy and regularity in configuration bits between different contexts. Under a constraint of the same number of contexts, an area of the proposed switch block is 59% of that of the conventional switch block.

Original languageEnglish
Title of host publicationARC 2005 - International Workshop on Applied Reconfigurable Computing 2005
Pages99-102
Number of pages4
Publication statusPublished - 2005 Dec 1
EventInternational Workshop on Applied Reconfigurable Computing 2005, ARC 2005 - Algarve, Portugal
Duration: 2005 Feb 222005 Feb 23

Other

OtherInternational Workshop on Applied Reconfigurable Computing 2005, ARC 2005
CountryPortugal
CityAlgarve
Period05/2/2205/2/23

Keywords

  • Ferroelectric-based functional pass-gates
  • Reconfigurable hardware

ASJC Scopus subject areas

  • Computational Theory and Mathematics
  • Applied Mathematics

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    Chong, W., Hariyama, M., & Kameyama, M. (2005). Novel switch-block architecture using reconfigurable context memory for multi-context FPGAs. In ARC 2005 - International Workshop on Applied Reconfigurable Computing 2005 (pp. 99-102)