Novel NAND DRAM with surrounding gate transistor (SGT)-type gain cell

Hiroki Nakamura, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka

Research output: Contribution to journalArticlepeer-review

Abstract

A novel NAND DRAM with SGT-type gain cell is proposed. This SGT-type gain cell structure is composed of an SGT and SGT-type capacitor slacked vertically on a planar read transistor. Its cell size can be reduced to 4F2 since it can be arranged to have the cross-point configuration. Therefore, high-density DRAM is achieved. Since it operates as a gain cell, it is possible to obtain sufficient signal charge regardless of the stored amount. Therefore, the proposed DRAM operates at low supply voltages, where it is difficult to obtain sufficient read-out voltage in conventional DRAM. It is shown that the novel NAND DRAM with SGT-type gain cell achieves high-density and low-voltage operation.

Original languageEnglish
Pages (from-to)1-8
Number of pages8
JournalElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume87
Issue number7
DOIs
Publication statusPublished - 2004 Jul 1

Keywords

  • Low-voltage operation
  • NAND DRAM
  • SGT-type gain cell
  • Surrounding gate transistor (SGT)

ASJC Scopus subject areas

  • Physics and Astronomy(all)
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Novel NAND DRAM with surrounding gate transistor (SGT)-type gain cell'. Together they form a unique fingerprint.

Cite this