Novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET

K. Murata, T. Otsuji, M. Ohhata, M. Togashi, E. Sano, M. Suzuki

Research output: Contribution to conferencePaperpeer-review

17 Citations (Scopus)

Abstract

This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs SCFL Logic. We reveal the high-speed operation mechanism of HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series gated master slave flip-flops and HLO-FFs based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision ICs confirm the accuracy of our analytical method and the high speed operation of a HLO-FF decision circuit at 19 Gb/s.

Original languageEnglish
Pages193-196
Number of pages4
Publication statusPublished - 1994 Dec 1
Externally publishedYes
EventProceedingsof the 1994 IEEE GaAs IC Symposium - Philadelphia, PA, USA
Duration: 1994 Oct 161994 Oct 19

Other

OtherProceedingsof the 1994 IEEE GaAs IC Symposium
CityPhiladelphia, PA, USA
Period94/10/1694/10/19

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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