Novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET

K. Murata; T. Otsuji; M. Ohhata; M. Togashi; E. Sano; M. Suzuki

Novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET

K. Murata, T. Otsuji, M. Ohhata, M. Togashi, E. Sano, M. Suzuki

Research output: Contribution to conference › Paper › peer-review

Abstract

This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs SCFL Logic. We reveal the high-speed operation mechanism of HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series gated master slave flip-flops and HLO-FFs based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision ICs confirm the accuracy of our analytical method and the high speed operation of a HLO-FF decision circuit at 19 Gb/s.

Original language	English
Pages	193-196
Number of pages	4
Publication status	Published - 1994 Dec 1
Externally published	Yes
Event	Proceedingsof the 1994 IEEE GaAs IC Symposium - Philadelphia, PA, USA Duration: 1994 Oct 16 → 1994 Oct 19

Other

Other	Proceedingsof the 1994 IEEE GaAs IC Symposium
City	Philadelphia, PA, USA
Period	94/10/16 → 94/10/19

ASJC Scopus subject areas

Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET'. Together they form a unique fingerprint.

Cite this

Novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET. / Murata, K.; Otsuji, T.; Ohhata, M.; Togashi, M.; Sano, E.; Suzuki, M.

1994. 193-196 Paper presented at Proceedingsof the 1994 IEEE GaAs IC Symposium, Philadelphia, PA, USA, .

Research output: Contribution to conference › Paper › peer-review

@conference{04ed2732c83f4632b7cfeaf5835fa992,

title = "Novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET",

abstract = "This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs SCFL Logic. We reveal the high-speed operation mechanism of HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series gated master slave flip-flops and HLO-FFs based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision ICs confirm the accuracy of our analytical method and the high speed operation of a HLO-FF decision circuit at 19 Gb/s.",

author = "K. Murata and T. Otsuji and M. Ohhata and M. Togashi and E. Sano and M. Suzuki",

year = "1994",

month = dec,

day = "1",

language = "English",

pages = "193--196",

note = "Proceedingsof the 1994 IEEE GaAs IC Symposium ; Conference date: 16-10-1994 Through 19-10-1994",

}

TY - CONF

T1 - Novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET

AU - Murata, K.

AU - Otsuji, T.

AU - Ohhata, M.

AU - Togashi, M.

AU - Sano, E.

AU - Suzuki, M.

PY - 1994/12/1

Y1 - 1994/12/1

N2 - This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs SCFL Logic. We reveal the high-speed operation mechanism of HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series gated master slave flip-flops and HLO-FFs based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision ICs confirm the accuracy of our analytical method and the high speed operation of a HLO-FF decision circuit at 19 Gb/s.

AB - This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs SCFL Logic. We reveal the high-speed operation mechanism of HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series gated master slave flip-flops and HLO-FFs based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision ICs confirm the accuracy of our analytical method and the high speed operation of a HLO-FF decision circuit at 19 Gb/s.

UR - http://www.scopus.com/inward/record.url?scp=0028714060&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0028714060&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0028714060

SP - 193

EP - 196

T2 - Proceedingsof the 1994 IEEE GaAs IC Symposium

Y2 - 16 October 1994 through 19 October 1994

ER -

Novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET

Abstract

Other

ASJC Scopus subject areas

Other files and links

Cite this