Abstract
This paper describes a novel high-speed flip-flop circuit named the High-speed Latching Operation Flip-Flop (HLO-FF) for GaAs SCFL Logic. We reveal the high-speed operation mechanism of HLO-FF using newly proposed analytical propagation delay time expressions. A design methodology for series gated master slave flip-flops and HLO-FFs based on these expressions is also proposed. A SPICE simulation and the fabrication of two decision ICs confirm the accuracy of our analytical method and the high speed operation of a HLO-FF decision circuit at 19 Gb/s.
| Original language | English |
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| Pages | 193-196 |
| Number of pages | 4 |
| Publication status | Published - 1994 Dec 1 |
| Externally published | Yes |
| Event | Proceedingsof the 1994 IEEE GaAs IC Symposium - Philadelphia, PA, USA Duration: 1994 Oct 16 → 1994 Oct 19 |
Other
| Other | Proceedingsof the 1994 IEEE GaAs IC Symposium |
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| City | Philadelphia, PA, USA |
| Period | 94/10/16 → 94/10/19 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering