M. Koyanagi, H. Sunami, N. Hashimoto, M. Ashikawa

Research output: Contribution to conferencePaper

58 Citations (Scopus)


A novel one transistor type MOS RAM cell is successfully developed and achieves a higher degree of integration than realized to date with conventional RAM's. This cell provides remarkable area reduction and/or an increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor. It is called a stacked capacitor RAM (STC RAM) cell. This new cell has a triple level poly-Si structure of poly-Si word lines and Al bit lines. The stacked capacitor is composed of a poly-Si - Si//3N//4 - poly-Si structure. A 256 bit STC MOS RAM is fabricated with 3 mu m technology and operates successfully. The STC RAM cell area, 52. 5 mu m**2, is remarkably smaller than the cell area of conventional RAM's with double level poly-Si gate structure, 160 mu m**2. The text of this paper is in digest form.

Original languageEnglish
Number of pages4
Publication statusPublished - 1978
EventInt Electron Devices Meet (IEDM), 24th, Tech Dig - Washington, DC, USA
Duration: 1978 Dec 41978 Dec 6


OtherInt Electron Devices Meet (IEDM), 24th, Tech Dig
CityWashington, DC, USA

ASJC Scopus subject areas

  • Engineering(all)

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    Koyanagi, M., Sunami, H., Hashimoto, N., & Ashikawa, M. (1978). NOVEL HIGH DENSITY, STACKED CAPACITOR MOS RAM.. 348-351. Paper presented at Int Electron Devices Meet (IEDM), 24th, Tech Dig, Washington, DC, USA, .