Novel high density, stacked capacitor MOS RAM

Mitsumasa Koyanagi, Hideo Sunami, Norikazu Hashimoto

Research output: Contribution to journalArticlepeer-review


A novel one transistor type MOS RAM cell is successfully developed and achieves a higher degree of integration than realized to date with conventional RAM's. This cell provides a remarkablearea reduction and/or an increase in storage capacitance by stacking the main portion of the storage capacitor on the address transistor. It is called a stacked capacitor RAM (STC RAM) cell. This STC cell has a triple level poly-Si structure which consists of poly-Si word line and Al bit line. The stacked capacitor is composed of the poly-Si–Si3N4–poly-Si structure. A 256 bit STC MOS RAM is fabricated with 3 °m technology and operates successfully.TheSTC RAM cell area, 52.5 °m2, is remarkably smaller than the cell area of conventional RAM’s with double level poly-Si gate structures, 160 °m2. The charge stored timein the new STC MOS RAM normally ranged from 0.1 sec to 1 sec at room temperature.

Original languageEnglish
Pages (from-to)237-245
Number of pages9
JournalJapanese journal of applied physics
Publication statusPublished - 1979 Jan
Externally publishedYes

ASJC Scopus subject areas

  • Engineering(all)
  • Physics and Astronomy(all)


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