A new MOS RAM cell was successfully developed having a higher degree of integration than realized to date with conventional RAM's. This cell provides a remarkable area reduction and/or an increase in storage capacitance, by stacking the main portion of the storage capacitor on the address transistor. It is called a stacked capacitor RAM (STC RAM) cell. This STC cell has a triple level poly-Si structure which consists of poly-Si word line and Al bit line. The stacked capacitor is composed of the poly-Si-Si//3 N//4 -poly-Si structure. A 256-bit STC MOS RAM is fabricated with 3 mu m technology and operates successfully. The STC RAM cell area, 52. 5 mu m**2 , is remarkably smaller than the cell area of conventional RAM's with double level poly-Si gate structures, 160 mu m**2 . The charge stored time in the new STC MOS RAM normally ranged from 0. 1 sec to 1 sec at room temperature.
|Number of pages||8|
|Publication status||Published - 1979 Jan 1|
|Event||Proc Conf Solid State Devices 10th - Tokyo, Jpn|
Duration: 1978 Aug 29 → 1978 Aug 30
|Other||Proc Conf Solid State Devices 10th|
|Period||78/8/29 → 78/8/30|
ASJC Scopus subject areas