Mitsumasa Koyanagi, Hideo Sunami, Norikazu Hashimoto

Research output: Contribution to conferencePaperpeer-review

6 Citations (Scopus)


A new MOS RAM cell was successfully developed having a higher degree of integration than realized to date with conventional RAM's. This cell provides a remarkable area reduction and/or an increase in storage capacitance, by stacking the main portion of the storage capacitor on the address transistor. It is called a stacked capacitor RAM (STC RAM) cell. This STC cell has a triple level poly-Si structure which consists of poly-Si word line and Al bit line. The stacked capacitor is composed of the poly-Si-Si//3 N//4 -poly-Si structure. A 256-bit STC MOS RAM is fabricated with 3 mu m technology and operates successfully. The STC RAM cell area, 52. 5 mu m**2 , is remarkably smaller than the cell area of conventional RAM's with double level poly-Si gate structures, 160 mu m**2 . The charge stored time in the new STC MOS RAM normally ranged from 0. 1 sec to 1 sec at room temperature.

Original languageEnglish
Number of pages8
Publication statusPublished - 1979 Jan 1
EventProc Conf Solid State Devices 10th - Tokyo, Jpn
Duration: 1978 Aug 291978 Aug 30


OtherProc Conf Solid State Devices 10th
CityTokyo, Jpn

ASJC Scopus subject areas

  • Engineering(all)

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