Recently, we proposed a novel 3-D vertical floating gate (FG)-type nand Flash memory cell array using the separated-sidewall control gate (CG) (S-SCG). This novel cell consists of one cylindrical FG with line-type CG and S-SCG structures. For simplifying the process flow, we realized the common S-SCG lines by using the prestacked polysilicon layer, through which variable medium voltages are applied not only to control the electrically inverted S/D region but also to assist the program and erase operations. In this paper, we successfully demonstrate the normal Flash cell operation and show its superior performances in comparison with the recent 3-D FG nand cells by using the cylindrical device simulation. It is shown that the proposed cell can realize the highest CG coupling ratio, low-voltage cell operations of program with 15 V at V th = 4 V and erase with 14 V at V th = -3 V, good retention-mode electric field, and sufficient read-mode on-current margin. Moreover, the proposed S-SCG cell array can fully suppress both the interference effects and the disturbance problems at the same time by removing the direct coupling effects in the same cell string, which are the most critical problems of the recent 3-D vertical stacked cell structures. Above all, the proposed cell array has good potential for terabit 3-D vertical nand Flash cell array with highly reliable multilevel cell operation.
- 3-D vertical stacked cell
- Cylindrical floating gate (FG)
- nand Flash memory
- separated-sidewall control gate (CG) (SCG) (S-SCG)
ASJC Scopus subject areas
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering