Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating

Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Citations (Scopus)

Abstract

Nonvolatile logic-in-memory (NV-LIM) architecture [1], where magnetic tunnel junction (MTJ) devices [2] are distributed over a CMOS logic-circuit plane, has the potential of overcoming the serious power-consumption problem that has rapidly become a dominant constraint on the performance improvement of today's VLSI processors. Normally-off and instant-on capabilities with a small area penalty due to non-volatility and three-dimensional-stackability of MTJ devices in the above structure allow us to apply a power-gating technique in a fine temporal granularity, which can perfectly eliminate wasted power dissipation due to leakage current. The impact of embedding nonvolatile memory devices into a logic circuit was, however, demonstrated by using only small fabricated primitive logic-circuit elements [3], memory-like structures such as FPGA [4], or circuit simulation because of the lack of an established MTJ-oriented design flow reflecting the chip-fabrication environment, while larger-capacity and/or high-speed-access MRAM has been increasingly developed. In this paper, we present an MTJ/MOS-hybrid video coding hardware that uses a cycle-based power-gating technique for a practical-scale MTJ-based NV-LIM LSI, which is fully designed using the established semi-automated MTJ-oriented design flow.

Original languageEnglish
Title of host publication2013 IEEE International Solid-State Circuits Conference, ISSCC 2013 - Digest of Technical Papers
Pages194-195
Number of pages2
DOIs
Publication statusPublished - 2013 Apr 29
Event2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013 - San Francisco, CA, United States
Duration: 2013 Feb 172013 Feb 21

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume56
ISSN (Print)0193-6530

Other

Other2013 60th IEEE International Solid-State Circuits Conference, ISSCC 2013
CountryUnited States
CitySan Francisco, CA
Period13/2/1713/2/21

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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