Nonvolatile field-programmable gate array using a standard-cell-based design flow

Daisuke Suzuki, Takahiro Hanyu

Research output: Contribution to journalReview articlepeer-review

Abstract

A nonvolatile field-programmable gate array (NV-FPGA), where the circuit-configuration information still remains without power supply, offers a powerful solution against the standby power issue. In this paper, an NV-FPGA is proposed where the programmable logic and interconnect function blocks are described in a hardware description language and are pushed through a standard-cell-based design flow with nonvolatile flip-flops. The use of the standard-cell-based design flow makes it possible to migrate any arbitrary process technology and to perform architecture-level simulation with physical information. As a typical example, the proposed NV-FPGA is designed under 55nm CMOS/100nm magnetic tunnel junction (MTJ) technologies, and the performance of the proposed NV-FPGA is evaluated in comparison with that of a CMOS-only volatile FPGA.

Original languageEnglish
Pages (from-to)1111-1120
Number of pages10
JournalIEICE Transactions on Information and Systems
VolumeE104D
Issue number8
DOIs
Publication statusPublished - 2021

Keywords

  • FPGA
  • Hardware description language
  • Logic synthesis
  • Nonvolatile logic
  • Standard-cell-based design

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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