Non-volatile multi-context FPGAs using hybrid multiple-valued/binary context switching signals

Masanori Hariyama, S. Ishihara, N. Idobata, M. Kameyama

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

Multi-context (MC) FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant overhead in area and power consumption. This paper presents two key technologies. The first is a floating-gate-MOS functional pass gate that merges storage and switching functions area-efficiently. The second is the use of a hybrid multiple-valued/binary context switching signal that eliminates redundancy of a conventional MC-switch with high scalability. The transistor count of the proposed MC-switch is reduced to 7% in comparison with that of a SRAM-based one. Although the FGFP-based MC-switch is compact, it has a large data path delay. Using a ferroelectric-based functional pass-gate, the delay of the proposed MC-switch is same as that of the SRAM-Based one while reducing the transistor count to 86%.

Original languageEnglish
Title of host publicationProceedings of the 2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
Pages309-310
Number of pages2
Publication statusPublished - 2008 Dec 1
Event2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008 - Las Vegas, NV, United States
Duration: 2008 Jul 142008 Jul 17

Other

Other2008 International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA 2008
CountryUnited States
CityLas Vegas, NV
Period08/7/1408/7/17

Keywords

  • Ferro-electric capacitor
  • Floating MOS transistor
  • FPGA

ASJC Scopus subject areas

  • Computer Science Applications
  • Hardware and Architecture
  • Software

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